From: Marc Zyngier <maz@kernel.org>
To: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org,
kvm@vger.kernel.org
Cc: Joey Gouly <joey.gouly@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Oliver Upton <oliver.upton@linux.dev>,
Zenghui Yu <yuzenghui@huawei.com>
Subject: [PATCH v2 08/16] KVM: arm64: Expand valid block mappings to FEAT_LPA/LPA2 support
Date: Mon, 15 Sep 2025 12:44:43 +0100 [thread overview]
Message-ID: <20250915114451.660351-9-maz@kernel.org> (raw)
In-Reply-To: <20250915114451.660351-1-maz@kernel.org>
With 52bit PAs, block mappings can exist at different levels (such
as level 0 for 4kB pages, or level 1 for 16kB and 64kB pages).
Account for this in walk_s1().
Signed-off-by: Marc Zyngier <maz@kernel.org>
---
arch/arm64/kvm/at.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/kvm/at.c b/arch/arm64/kvm/at.c
index 1c2f7719b6cbb..fad9d7828d7b6 100644
--- a/arch/arm64/kvm/at.c
+++ b/arch/arm64/kvm/at.c
@@ -448,11 +448,11 @@ static int walk_s1(struct kvm_vcpu *vcpu, struct s1_walk_info *wi,
switch (BIT(wi->pgshift)) {
case SZ_4K:
- valid_block = level == 1 || level == 2;
+ valid_block = level == 1 || level == 2 || (wi->pa52bit && level == 0);
break;
case SZ_16K:
case SZ_64K:
- valid_block = level == 2;
+ valid_block = level == 2 || (wi->pa52bit && level == 1);
break;
}
--
2.39.2
next prev parent reply other threads:[~2025-09-15 11:44 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-15 11:44 [PATCH v2 00/16] KVM: arm64: TTW reporting on SEA and 52bit PA in S1 PTW Marc Zyngier
2025-09-15 11:44 ` [PATCH v2 01/16] KVM: arm64: Add helper computing the state of 52bit PA support Marc Zyngier
2025-09-15 11:44 ` [PATCH v2 02/16] KVM: arm64: Account for 52bit when computing maximum OA Marc Zyngier
2025-09-15 11:44 ` [PATCH v2 03/16] KVM: arm64: Compute 52bit TTBR address and alignment Marc Zyngier
2025-09-15 11:44 ` [PATCH v2 04/16] KVM: arm64: Decouple output address from the PT descriptor Marc Zyngier
2025-09-15 11:44 ` [PATCH v2 05/16] KVM: arm64: Pass the walk_info structure to compute_par_s1() Marc Zyngier
2025-09-15 11:44 ` [PATCH v2 06/16] KVM: arm64: Compute shareability for LPA2 Marc Zyngier
2025-09-19 21:58 ` Oliver Upton
2025-09-15 11:44 ` [PATCH v2 07/16] KVM: arm64: Populate PAR_EL1 with 52bit addresses Marc Zyngier
2025-09-19 22:00 ` Oliver Upton
2025-09-20 9:27 ` Marc Zyngier
2025-09-15 11:44 ` Marc Zyngier [this message]
2025-09-15 11:44 ` [PATCH v2 09/16] KVM: arm64: Report faults from S1 walk setup at the expected start level Marc Zyngier
2025-09-15 11:44 ` [PATCH v2 10/16] KVM: arm64: Allow use of S1 PTW for non-NV vcpus Marc Zyngier
2025-09-19 22:27 ` Oliver Upton
2025-09-20 9:24 ` Marc Zyngier
2025-09-15 11:44 ` [PATCH v2 11/16] KVM: arm64: Allow EL1 control registers to be accessed from the CPU state Marc Zyngier
2025-09-15 11:44 ` [PATCH v2 12/16] KVM: arm64: Don't switch MMU on translation from non-NV context Marc Zyngier
2025-09-15 11:44 ` [PATCH v2 13/16] KVM: arm64: Add filtering hook to S1 page table walk Marc Zyngier
2025-09-15 11:44 ` [PATCH v2 14/16] KVM: arm64: Add S1 IPA to page table level walker Marc Zyngier
2025-09-19 22:31 ` Oliver Upton
2025-09-15 11:44 ` [PATCH v2 15/16] KVM: arm64: Populate level on S1PTW SEA injection Marc Zyngier
2025-09-15 11:44 ` [PATCH v2 16/16] KVM: arm64: selftest: Expand external_aborts test to look for TTW levels Marc Zyngier
2025-09-19 22:36 ` Oliver Upton
2025-09-19 22:37 ` [PATCH v2 00/16] KVM: arm64: TTW reporting on SEA and 52bit PA in S1 PTW Oliver Upton
2025-09-21 11:00 ` Marc Zyngier
2025-09-21 10:57 ` Marc Zyngier
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