[kvm-unit-tests PATCH 09/17] x86/vmx: switch to new vmx.h EPT capability and memory type defs

[Jon Kohler <jon@nutanix.com>]

Migrate to new vmx.h's EPT definitions for capability and memory type,
which makes it easier to grok from one code base to another.

Pickup new lib/x86/msr.h definitions for memory types, from:
e7e80b6 ("x86/cpu: KVM: Add common defines for architectural memory types (PAT, MTRRs, etc.)")

No functional change intended.

Signed-off-by: Jon Kohler <jon@nutanix.com>

---
 lib/x86/msr.h   | 14 ++++++++++++++
 x86/vmx.c       | 18 +++++++++---------
 x86/vmx.h       | 33 ++++++++++-----------------------
 x86/vmx_tests.c | 14 +++++++-------
 4 files changed, 40 insertions(+), 39 deletions(-)

diff --git a/lib/x86/msr.h b/lib/x86/msr.h
index cc4cb855..06a3b34a 100644
--- a/lib/x86/msr.h
+++ b/lib/x86/msr.h
@@ -31,6 +31,20 @@
 #define EFER_LMSLE		(1<<_EFER_LMSLE)
 #define EFER_FFXSR		(1<<_EFER_FFXSR)
 
+/*
+ * Architectural memory types that are common to MTRRs, PAT, VMX MSRs, etc.
+ * Most MSRs support/allow only a subset of memory types, but the values
+ * themselves are common across all relevant MSRs.
+ */
+#define X86_MEMTYPE_UC		0ull	/* Uncacheable, a.k.a. Strong Uncacheable */
+#define X86_MEMTYPE_WC		1ull	/* Write Combining */
+/* RESERVED			2 */
+/* RESERVED			3 */
+#define X86_MEMTYPE_WT		4ull	/* Write Through */
+#define X86_MEMTYPE_WP		5ull	/* Write Protected */
+#define X86_MEMTYPE_WB		6ull	/* Write Back */
+#define X86_MEMTYPE_UC_MINUS	7ull	/* Weak Uncacheabled (PAT only) */
+
 /* Intel MSRs. Some also available on other CPUs */
 #define MSR_IA32_SPEC_CTRL		0x00000048
 #define SPEC_CTRL_IBRS			BIT(0)
diff --git a/x86/vmx.c b/x86/vmx.c
index a3c6c60b..df9a23c7 100644
--- a/x86/vmx.c
+++ b/x86/vmx.c
@@ -1641,15 +1641,15 @@ static void test_vmx_caps(void)
 	       "MSR_IA32_VMX_VMCS_ENUM");
 
 	fixed0 = -1ull;
-	fixed0 &= ~(EPT_CAP_EXEC_ONLY |
-		    EPT_CAP_PWL4 |
-		    EPT_CAP_PWL5 |
-		    EPT_CAP_UC |
-		    EPT_CAP_WB |
-		    EPT_CAP_2M_PAGE |
-		    EPT_CAP_1G_PAGE |
-		    EPT_CAP_INVEPT |
-		    EPT_CAP_AD_FLAG |
+	fixed0 &= ~(VMX_EPT_EXECUTE_ONLY_BIT |
+		    VMX_EPT_PAGE_WALK_4_BIT |
+		    VMX_EPT_PAGE_WALK_5_BIT |
+		    VMX_EPTP_UC_BIT |
+		    VMX_EPTP_WB_BIT |
+		    VMX_EPT_2MB_PAGE_BIT |
+		    VMX_EPT_1GB_PAGE_BIT |
+		    VMX_EPT_INVEPT_BIT |
+		    VMX_EPT_AD_BIT |
 		    EPT_CAP_ADV_EPT_INFO |
 		    EPT_CAP_INVEPT_SINGLE |
 		    EPT_CAP_INVEPT_ALL |
diff --git a/x86/vmx.h b/x86/vmx.h
index 65012e0e..4d13ad91 100644
--- a/x86/vmx.h
+++ b/x86/vmx.h
@@ -571,27 +571,14 @@ enum Intr_type {
 #define EPTP_RESERV_BITS_MASK	0x1ful
 #define EPTP_RESERV_BITS_SHIFT	0x7ul
 
-#define EPT_MEM_TYPE_UC		0ul
 #define EPT_MEM_TYPE_WC		1ul
 #define EPT_MEM_TYPE_WT		4ul
 #define EPT_MEM_TYPE_WP		5ul
-#define EPT_MEM_TYPE_WB		6ul
 
 #define EPT_LARGE_PAGE		(1ul << 7)
-#define EPT_MEM_TYPE_SHIFT	3ul
-#define EPT_MEM_TYPE_MASK	0x7ul
 #define EPT_IGNORE_PAT		(1ul << 6)
 #define EPT_SUPPRESS_VE		(1ull << 63)
 
-#define EPT_CAP_EXEC_ONLY	(1ull << 0)
-#define EPT_CAP_PWL4		(1ull << 6)
-#define EPT_CAP_PWL5		(1ull << 7)
-#define EPT_CAP_UC		(1ull << 8)
-#define EPT_CAP_WB		(1ull << 14)
-#define EPT_CAP_2M_PAGE		(1ull << 16)
-#define EPT_CAP_1G_PAGE		(1ull << 17)
-#define EPT_CAP_INVEPT		(1ull << 20)
-#define EPT_CAP_AD_FLAG		(1ull << 21)
 #define EPT_CAP_ADV_EPT_INFO	(1ull << 22)
 #define EPT_CAP_INVEPT_SINGLE	(1ull << 25)
 #define EPT_CAP_INVEPT_ALL	(1ull << 26)
@@ -662,12 +649,12 @@ extern union vmx_ept_vpid  ept_vpid;
 
 static inline bool ept_2m_supported(void)
 {
-	return ept_vpid.val & EPT_CAP_2M_PAGE;
+	return ept_vpid.val & VMX_EPT_2MB_PAGE_BIT;
 }
 
 static inline bool ept_1g_supported(void)
 {
-	return ept_vpid.val & EPT_CAP_1G_PAGE;
+	return ept_vpid.val & VMX_EPT_1GB_PAGE_BIT;
 }
 
 static inline bool ept_huge_pages_supported(int level)
@@ -682,31 +669,31 @@ static inline bool ept_huge_pages_supported(int level)
 
 static inline bool ept_execute_only_supported(void)
 {
-	return ept_vpid.val & EPT_CAP_EXEC_ONLY;
+	return ept_vpid.val & VMX_EPT_EXECUTE_ONLY_BIT;
 }
 
 static inline bool ept_ad_bits_supported(void)
 {
-	return ept_vpid.val & EPT_CAP_AD_FLAG;
+	return ept_vpid.val & VMX_EPT_AD_BIT;
 }
 
 static inline bool is_4_level_ept_supported(void)
 {
-	return ept_vpid.val & EPT_CAP_PWL4;
+	return ept_vpid.val & VMX_EPT_PAGE_WALK_4_BIT;
 }
 
 static inline bool is_5_level_ept_supported(void)
 {
-	return ept_vpid.val & EPT_CAP_PWL5;
+	return ept_vpid.val & VMX_EPT_PAGE_WALK_5_BIT;
 }
 
 static inline bool is_ept_memtype_supported(int type)
 {
-	if (type == EPT_MEM_TYPE_UC)
-		return ept_vpid.val & EPT_CAP_UC;
+	if (type == VMX_EPTP_MT_UC)
+		return ept_vpid.val & VMX_EPTP_UC_BIT;
 
-	if (type == EPT_MEM_TYPE_WB)
-		return ept_vpid.val & EPT_CAP_WB;
+	if (type == VMX_EPTP_MT_WB)
+		return ept_vpid.val & VMX_EPTP_WB_BIT;
 
 	return false;
 }
diff --git a/x86/vmx_tests.c b/x86/vmx_tests.c
index f7ea411f..5ca4b79b 100644
--- a/x86/vmx_tests.c
+++ b/x86/vmx_tests.c
@@ -1050,7 +1050,7 @@ static int __setup_ept(u64 hpa, bool enable_ad)
 		printf("\tEPT is not supported\n");
 		return 1;
 	}
-	if (!is_ept_memtype_supported(EPT_MEM_TYPE_WB)) {
+	if (!is_ept_memtype_supported(VMX_EPTP_MT_WB)) {
 		printf("\tWB memtype for EPT walks not supported\n");
 		return 1;
 	}
@@ -1062,7 +1062,7 @@ static int __setup_ept(u64 hpa, bool enable_ad)
 		return 1;
 	}
 
-	eptp = EPT_MEM_TYPE_WB;
+	eptp = VMX_EPTP_MT_WB;
 	eptp |= (3 << EPTP_PG_WALK_LEN_SHIFT);
 	eptp |= hpa;
 	if (enable_ad)
@@ -1385,7 +1385,7 @@ static int ept_exit_handler_common(union exit_reason exit_reason, bool have_ad)
 				    VMX_EPT_READABLE_MASK |
 				    VMX_EPT_WRITABLE_MASK |
 				    VMX_EPT_EXECUTABLE_MASK |
-				    (2 << EPT_MEM_TYPE_SHIFT));
+				    (2 << VMX_EPT_MT_EPTE_SHIFT));
 			invept(INVEPT_SINGLE, eptp);
 			break;
 		case 3:
@@ -4838,10 +4838,10 @@ static void test_ept_eptp(void)
 	eptp = vmcs_read(EPTP);
 
 	for (i = 0; i < 8; i++) {
-		eptp = (eptp & ~EPT_MEM_TYPE_MASK) | i;
+		eptp = (eptp & ~VMX_EPTP_MT_MASK) | i;
 		vmcs_write(EPTP, eptp);
-		report_prefix_pushf("Enable-EPT enabled; EPT memory type %lu",
-		    eptp & EPT_MEM_TYPE_MASK);
+		report_prefix_pushf("Enable-EPT enabled; EPT memory type %llu",
+				    eptp & VMX_EPTP_MT_MASK);
 		if (is_ept_memtype_supported(i))
 			test_vmx_valid_controls();
 		else
@@ -4849,7 +4849,7 @@ static void test_ept_eptp(void)
 		report_prefix_pop();
 	}
 
-	eptp = (eptp & ~EPT_MEM_TYPE_MASK) | 6ul;
+	eptp = (eptp & ~VMX_EPTP_MT_MASK) | 6ul;
 
 	/*
 	 * Page walk length (bits 5:3).  Note, the value in VMCS.EPTP "is 1
-- 
2.43.0