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Sat, 20 Sep 2025 13:39:01 -0700 (PDT) From: Andrew Jones To: iommu@lists.linux.dev, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: jgg@nvidia.com, zong.li@sifive.com, tjeznach@rivosinc.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, anup@brainfault.org, atish.patra@linux.dev, tglx@linutronix.de, alex.williamson@redhat.com, paul.walmsley@sifive.com, palmer@dabbelt.com, alex@ghiti.fr Subject: [RFC PATCH v2 07/18] iommu/riscv: Export phys_to_ppn and ppn_to_phys Date: Sat, 20 Sep 2025 15:38:57 -0500 Message-ID: <20250920203851.2205115-27-ajones@ventanamicro.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250920203851.2205115-20-ajones@ventanamicro.com> References: <20250920203851.2205115-20-ajones@ventanamicro.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The riscv iommu uses a specific set of bits for PPNs (53:10). Export the translation functions so iommu-ir can use them as well. Signed-off-by: Andrew Jones --- drivers/iommu/riscv/iommu-bits.h | 4 ++++ drivers/iommu/riscv/iommu.c | 14 +++++--------- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/iommu/riscv/iommu-bits.h b/drivers/iommu/riscv/iommu-bits.h index d72b982cf9bf..d3d98dbed709 100644 --- a/drivers/iommu/riscv/iommu-bits.h +++ b/drivers/iommu/riscv/iommu-bits.h @@ -36,6 +36,10 @@ #define RISCV_IOMMU_ATP_PPN_FIELD GENMASK_ULL(43, 0) #define RISCV_IOMMU_ATP_MODE_FIELD GENMASK_ULL(63, 60) +/* RISC-V IOMMU PPN <> PHYS address conversions, PHYS <=> PPN[53:10] */ +#define riscv_iommu_phys_to_ppn(pa) (((pa) >> 2) & (((1ULL << 44) - 1) << 10)) +#define riscv_iommu_ppn_to_phys(pn) (((pn) << 2) & (((1ULL << 44) - 1) << 12)) + /* 5.3 IOMMU Capabilities (64bits) */ #define RISCV_IOMMU_REG_CAPABILITIES 0x0000 #define RISCV_IOMMU_CAPABILITIES_VERSION GENMASK_ULL(7, 0) diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c index 7418e91d8edd..440c3eb6f15a 100644 --- a/drivers/iommu/riscv/iommu.c +++ b/drivers/iommu/riscv/iommu.c @@ -30,10 +30,6 @@ #define RISCV_IOMMU_DEF_CQ_COUNT 8192 #define RISCV_IOMMU_DEF_FQ_COUNT 4096 -/* RISC-V IOMMU PPN <> PHYS address conversions, PHYS <=> PPN[53:10] */ -#define phys_to_ppn(pa) (((pa) >> 2) & (((1ULL << 44) - 1) << 10)) -#define ppn_to_phys(pn) (((pn) << 2) & (((1ULL << 44) - 1) << 12)) - /* IOMMU PSCID allocation namespace. */ static DEFINE_IDA(riscv_iommu_pscids); #define RISCV_IOMMU_MAX_PSCID (BIT(20) - 1) @@ -165,7 +161,7 @@ static int riscv_iommu_queue_alloc(struct riscv_iommu_device *iommu, if (!queue->base) return -ENOMEM; - qb = phys_to_ppn(queue->phys) | + qb = riscv_iommu_phys_to_ppn(queue->phys) | FIELD_PREP(RISCV_IOMMU_QUEUE_LOG2SZ_FIELD, logsz); /* Update base register and read back to verify hw accepted our write */ @@ -608,7 +604,7 @@ static struct riscv_iommu_dc *riscv_iommu_get_dc(struct riscv_iommu_device *iomm do { ddt = READ_ONCE(*(unsigned long *)ddtp); if (ddt & RISCV_IOMMU_DDTE_V) { - ddtp = __va(ppn_to_phys(ddt)); + ddtp = __va(riscv_iommu_ppn_to_phys(ddt)); break; } @@ -616,7 +612,7 @@ static struct riscv_iommu_dc *riscv_iommu_get_dc(struct riscv_iommu_device *iomm if (!ptr) return NULL; - new = phys_to_ppn(__pa(ptr)) | RISCV_IOMMU_DDTE_V; + new = riscv_iommu_phys_to_ppn(__pa(ptr)) | RISCV_IOMMU_DDTE_V; old = cmpxchg_relaxed((unsigned long *)ddtp, ddt, new); if (old == ddt) { @@ -683,7 +679,7 @@ static int riscv_iommu_iodir_alloc(struct riscv_iommu_device *iommu) if (ddtp & RISCV_IOMMU_DDTP_BUSY) return -EBUSY; - iommu->ddt_phys = ppn_to_phys(ddtp); + iommu->ddt_phys = riscv_iommu_ppn_to_phys(ddtp); if (iommu->ddt_phys) iommu->ddt_root = devm_ioremap(iommu->dev, iommu->ddt_phys, PAGE_SIZE); @@ -730,7 +726,7 @@ static int riscv_iommu_iodir_set_mode(struct riscv_iommu_device *iommu, do { rq_ddtp = FIELD_PREP(RISCV_IOMMU_DDTP_IOMMU_MODE, rq_mode); if (rq_mode > RISCV_IOMMU_DDTP_IOMMU_MODE_BARE) - rq_ddtp |= phys_to_ppn(iommu->ddt_phys); + rq_ddtp |= riscv_iommu_phys_to_ppn(iommu->ddt_phys); riscv_iommu_writeq(iommu, RISCV_IOMMU_REG_DDTP, rq_ddtp); ddtp = riscv_iommu_read_ddtp(iommu); -- 2.49.0