From: Nikunj A Dadhania <nikunj@amd.com>
To: <seanjc@google.com>, <pbonzini@redhat.com>
Cc: <kvm@vger.kernel.org>, <thomas.lendacky@amd.com>,
<santosh.shukla@amd.com>, <bp@alien8.de>,
<joao.m.martins@oracle.com>, <nikunj@amd.com>,
<kai.huang@intel.com>
Subject: [PATCH v4 5/7] x86/cpufeatures: Add Page modification logging
Date: Mon, 13 Oct 2025 06:25:13 +0000 [thread overview]
Message-ID: <20251013062515.3712430-6-nikunj@amd.com> (raw)
In-Reply-To: <20251013062515.3712430-1-nikunj@amd.com>
Page modification logging(PML) is a hardware feature designed to track
guest modified memory pages. PML enables the hypervisor to identify which
pages in a guest's memory have been changed since the last checkpoint or
during live migration.
The PML feature is advertised via CPUID leaf 0x8000000A ECX[4] bit.
Acked-by: Borislav Petkov (AMD) <bp@alien8.de>
Signed-off-by: Nikunj A Dadhania <nikunj@amd.com>
---
arch/x86/include/asm/cpufeatures.h | 1 +
arch/x86/kernel/cpu/scattered.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index f1a9f40622cd..66db158caa13 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -228,6 +228,7 @@
#define X86_FEATURE_PVUNLOCK ( 8*32+20) /* PV unlock function */
#define X86_FEATURE_VCPUPREEMPT ( 8*32+21) /* PV vcpu_is_preempted function */
#define X86_FEATURE_TDX_GUEST ( 8*32+22) /* "tdx_guest" Intel Trust Domain Extensions Guest */
+#define X86_FEATURE_PML ( 8*32+23) /* AMD Page Modification logging */
/* Intel-defined CPU features, CPUID level 0x00000007:0 (EBX), word 9 */
#define X86_FEATURE_FSGSBASE ( 9*32+ 0) /* "fsgsbase" RDFSBASE, WRFSBASE, RDGSBASE, WRGSBASE instructions*/
diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c
index cf4ae822bcc0..1706b2f1ca4a 100644
--- a/arch/x86/kernel/cpu/scattered.c
+++ b/arch/x86/kernel/cpu/scattered.c
@@ -49,6 +49,7 @@ static const struct cpuid_bit cpuid_bits[] = {
{ X86_FEATURE_PROC_FEEDBACK, CPUID_EDX, 11, 0x80000007, 0 },
{ X86_FEATURE_AMD_FAST_CPPC, CPUID_EDX, 15, 0x80000007, 0 },
{ X86_FEATURE_MBA, CPUID_EBX, 6, 0x80000008, 0 },
+ { X86_FEATURE_PML, CPUID_ECX, 4, 0x8000000A, 0 },
{ X86_FEATURE_COHERENCY_SFW_NO, CPUID_EBX, 31, 0x8000001f, 0 },
{ X86_FEATURE_SMBA, CPUID_EBX, 2, 0x80000020, 0 },
{ X86_FEATURE_BMEC, CPUID_EBX, 3, 0x80000020, 0 },
--
2.48.1
next prev parent reply other threads:[~2025-10-13 6:26 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-13 6:25 [PATCH v4 0/7] KVM: SVM: Add Page Modification Logging (PML) support Nikunj A Dadhania
2025-10-13 6:25 ` [PATCH v4 1/7] KVM: x86: Carve out PML flush routine Nikunj A Dadhania
2025-10-14 22:04 ` Huang, Kai
2025-10-15 4:32 ` Nikunj A. Dadhania
2025-10-13 6:25 ` [PATCH v4 2/7] KVM: x86: Move PML page to common vcpu arch structure Nikunj A Dadhania
2025-10-13 6:25 ` [PATCH v4 3/7] KVM: x86: Move enable_pml variable to common x86 code Nikunj A Dadhania
2025-10-14 11:24 ` Huang, Kai
2025-10-14 19:22 ` Sean Christopherson
2025-10-14 20:47 ` Huang, Kai
2025-10-15 4:39 ` Nikunj A. Dadhania
2025-10-13 6:25 ` [PATCH v4 4/7] KVM: x86: Move nested CPU dirty logging logic to common code Nikunj A Dadhania
2025-10-14 11:34 ` Huang, Kai
2025-10-14 20:40 ` Huang, Kai
2025-10-14 21:24 ` Sean Christopherson
2025-10-14 21:37 ` Huang, Kai
2025-10-15 4:43 ` Nikunj A. Dadhania
2025-10-15 5:27 ` Huang, Kai
2025-10-15 9:06 ` Nikunj A. Dadhania
2025-10-15 21:37 ` Huang, Kai
2025-10-16 9:23 ` Nikunj A. Dadhania
2025-10-13 6:25 ` Nikunj A Dadhania [this message]
2025-10-13 6:25 ` [PATCH v4 6/7] KVM: SVM: Use BIT_ULL for 64-bit nested_ctl bit definitions Nikunj A Dadhania
2025-10-13 6:25 ` [PATCH v4 7/7] KVM: SVM: Add Page modification logging support Nikunj A Dadhania
2025-10-17 5:13 ` Huang, Kai
2025-11-06 9:28 ` Nikunj A. Dadhania
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