From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from outbound.st.icloud.com (p-east2-cluster1-host12-snip4-8.eps.apple.com [57.103.76.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 231C936CDE8 for ; Thu, 16 Oct 2025 16:57:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=57.103.76.61 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760633857; cv=none; b=Ktf2+5S4GMY/03LTsT5uFCojTqH6JKOD44IJj+3PBckXmVWStqCHjUtgEmHqarXdpOPEzI56Nti9Nu3zbP/2CwirCZrSppNsYLazlIpQNFkK/ijzGWxXEtAOifXGa7N0hR4qFbGvPe10gRjgzmIVVqTjyYtFmmIZwVmjnaez+Hc= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760633857; c=relaxed/simple; bh=F1ss0wXwcOBtU2iSGeR5odkhA8qQKqK7agU6A0hEQ90=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Q4qy6cGiYtbNX3pLwe0nj27WLe9N4p2zM4GdBjbIg5sphZezqGOZ0fcAC8NFtxPvAhF0BV+QllFzHTRWOR4XfTWRtiUFnkMzNKGg6qC92O0CU0BQKwNkjFp7GwVjbmlQbQMqHO26KAid/GnG30fLaOEVxFq9t0XP9+ODXidWNiY= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=unpredictable.fr; spf=pass smtp.mailfrom=unpredictable.fr; dkim=pass (2048-bit key) header.d=unpredictable.fr header.i=@unpredictable.fr header.b=B5ga6Scj; arc=none smtp.client-ip=57.103.76.61 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=unpredictable.fr Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=unpredictable.fr Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=unpredictable.fr header.i=@unpredictable.fr header.b="B5ga6Scj" Received: from outbound.st.icloud.com (unknown [127.0.0.2]) by p00-icloudmta-asmtp-us-east-1a-100-percent-2 (Postfix) with ESMTPS id 3C32B18001DF; Thu, 16 Oct 2025 16:57:30 +0000 (UTC) Dkim-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=unpredictable.fr; s=sig1; bh=PPb8dlcuMo+VEVLq+WaUpAP0KWKymP1yw5xY57lCVP0=; h=From:To:Subject:Date:Message-ID:MIME-Version:x-icloud-hme; b=B5ga6ScjYDJcp4chLCCMzwZXM5HFmxqDWr0WDic7bbMnIShjbiBha5isz2AY8vXKSnpYm2ZvZkQI0D6NqTi1C3oitgRCQv+X3vqVNPvvEz/PbOFeNyHWkaiK6pLfoCi+mQu3VN1+VwJiLTFbEsJCIp9O8ZC7DUNPz6rc0N4KfNyWnzG9NZBlXOBivv4z1e5/aENMbRDQRb8LHM3THzgbgLxaH8kBgMsNp10qyqqhUz5HK+NvreuToTcxds90AafOnUDTsAdSzc8a0M466qY0Aqa/STti0aAtdQ6Q0HlWuFSqqzxgEIj4c3pks1HmlN7kWBycB+LkkxgM4O1qkNph1w== mail-alias-created-date: 1752046281608 Received: from localhost.localdomain (unknown [17.42.251.67]) by p00-icloudmta-asmtp-us-east-1a-100-percent-2 (Postfix) with ESMTPSA id 00B2018001F5; Thu, 16 Oct 2025 16:56:27 +0000 (UTC) From: Mohamed Mediouni To: qemu-devel@nongnu.org Cc: Alexander Graf , Richard Henderson , Cameron Esfahani , Mads Ynddal , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Ani Sinha , Phil Dennis-Jordan , Mohamed Mediouni , Eduardo Habkost , Sunil Muthuswamy , "Michael S. Tsirkin" , Igor Mammedov , Paolo Bonzini , Yanan Wang , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , Shannon Zhao , kvm@vger.kernel.org, Peter Maydell , Marcel Apfelbaum , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Pedro Barbuda , Zhao Liu , Roman Bolshakov Subject: [PATCH v7 19/24] whpx: arm64: implement -cpu host Date: Thu, 16 Oct 2025 18:55:15 +0200 Message-ID: <20251016165520.62532-20-mohamed@unpredictable.fr> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20251016165520.62532-1-mohamed@unpredictable.fr> References: <20251016165520.62532-1-mohamed@unpredictable.fr> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDE2MDEyMiBTYWx0ZWRfXwdjSJzs1rTwc 5JZezxZVeS4vZ/DFL+kcOp/hhKuJAWDKaztS8nS+pySAjZ9nv+JTNqXI+rqDJa6NuIXSyZ+M00v blmsOZ2lidkzF3qzSXyp4SBJBHQumJ8d+oRn/tbhBfdsQ6/tGCGwOZGo41NqwkE0gYETrCVmgcj tgVU54TCaCn5MnLHG2eFHK6BRNjEtGI/kBKiIeqFPoFEPt3ggL18z8FZguCO22BPHjp1I2T+ena f5FbIWc/EeAvhFJlRzhwVGwRZQiUxP1wfMJ+Ar8NKPGwVV6uyOKvQUwS7g1qsEbBAbw0FQs8s= X-Proofpoint-GUID: sVQMnVfFfjUtUZMegn2p72e5WbNEvUkX X-Proofpoint-ORIG-GUID: sVQMnVfFfjUtUZMegn2p72e5WbNEvUkX X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-16_03,2025-10-13_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 spamscore=0 mlxscore=0 malwarescore=0 mlxlogscore=999 adultscore=0 clxscore=1030 phishscore=0 bulkscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.22.0-2506270000 definitions=main-2510160122 X-JNJ: AAAAAAAB1nTE+3xkoNq2R5/ncXr8cRUh9192cKza93LEdWCQb92JUvFgiawvUJXGy0O4fMoUr3M3FB0D6AD/1LXWe7IiafI2qRfd2Gw93a6oFT9+zs/mdA5Ss0UDPq5MmorZ8NPQ55RfnVYs8Dxb2qrI01dzMuv5eqfeHMMd54F+xey7+L6ztkqG2Papd7YCQwzDFqUcI3fD5p462+z1UtP0kOQ6qIMX2/1yfd/jHUdQT57br2i5Aa9fVFduTbxMe20gY1zA896OFzGqm1cB7MumBETMXPBaozB5pZGSHqqubDLIdSFpJkaZ1i2ocKrFx243GHSiE21tUwhKcQOfomG0IPgp7Y52wUFIvk0e7MVtx4zNouRno+47pftp3tDu8SdaUORbSzdW30WsZIraNFbCyP5p/l/ahRYabR/j6t0m98RSQocDfhVJoYEZ/2EkW7acj/T+CByLpkFqSU33OGgN2cLjgSv1kRbu8MtAqG9K528yrW1qLI+vtKhPWTO3vcqas4Or6hK5/2lStiijthcBZIovvyjC4Jrw38M2GVcVSBR2HsATS4z5Q8JHL5UPe3s+UO3bDfshBWy/hP7IFboLIZxTdnsQT67GVi7yKFW1sBjRtvcyTp5ysmA+b4CWjy8grjKuNeHP98BnKNuhZuZknKPwLb088UDmFwJgrqpUc+LfjMVL/Q+r5p5s3HjqoyBzWmwRoMSGa26b1kGq3hnNy/9rrZj7vURk+BaOJ/+++0DIgS3vq7RKfWX5VKZcuf9QPRK8enbETfvJ+C9LpjlZ0SHpcBhfFvkxogb8N0F28VDGOVYHLx1LDDTgRZviIRFcGQ9ReEk7J8cXClqiaY652L+mqQnYoBao0U0fWdVc0gufoEoeOCc3tfcSJyW89RQyMFQboKCU/P/foBE7B01qZZvqpbmlbcA= Logic to fetch MIDR_EL1 for cpu 0 adapted from: https://github.com/FEX-Emu/FEX/blob/e6de17e72ef03aa88ba14fa0ec13163061608c74/Source/Windows/Common/CPUFeatures.cpp#L62 Signed-off-by: Mohamed Mediouni --- hw/arm/virt.c | 2 +- target/arm/cpu64.c | 19 ++++--- target/arm/whpx/whpx-all.c | 104 +++++++++++++++++++++++++++++++++++++ target/arm/whpx_arm.h | 1 + 4 files changed, 119 insertions(+), 7 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index d3dd36908a..1904765db3 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -3312,7 +3312,7 @@ static void virt_machine_class_init(ObjectClass *oc, const void *data) #ifdef TARGET_AARCH64 ARM_CPU_TYPE_NAME("cortex-a53"), ARM_CPU_TYPE_NAME("cortex-a57"), -#if defined(CONFIG_KVM) || defined(CONFIG_HVF) +#if defined(CONFIG_KVM) || defined(CONFIG_HVF) || defined(CONFIG_WHPX) ARM_CPU_TYPE_NAME("host"), #endif /* CONFIG_KVM || CONFIG_HVF */ #endif /* TARGET_AARCH64 */ diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 26cf7e6dfa..3f00071081 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -26,10 +26,13 @@ #include "qemu/units.h" #include "system/kvm.h" #include "system/hvf.h" +#include "system/whpx.h" +#include "system/hw_accel.h" #include "system/qtest.h" #include "system/tcg.h" #include "kvm_arm.h" #include "hvf_arm.h" +#include "whpx_arm.h" #include "qapi/visitor.h" #include "hw/qdev-properties.h" #include "internals.h" @@ -522,7 +525,7 @@ void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) isar2 = FIELD_DP64(isar2, ID_AA64ISAR2, APA3, 0); isar2 = FIELD_DP64(isar2, ID_AA64ISAR2, GPA3, 0); - if (kvm_enabled() || hvf_enabled()) { + if (hwaccel_enabled()) { /* * Exit early if PAuth is enabled and fall through to disable it. * The algorithm selection properties are not present. @@ -599,10 +602,10 @@ void aarch64_add_pauth_properties(Object *obj) /* Default to PAUTH on, with the architected algorithm on TCG. */ qdev_property_add_static(DEVICE(obj), &arm_cpu_pauth_property); - if (kvm_enabled() || hvf_enabled()) { + if (hwaccel_enabled()) { /* * Mirror PAuth support from the probed sysregs back into the - * property for KVM or hvf. Is it just a bit backward? Yes it is! + * property for HW accel. Is it just a bit backward? Yes it is! * Note that prop_pauth is true whether the host CPU supports the * architected QARMA5 algorithm or the IMPDEF one. We don't * provide the separate pauth-impdef property for KVM or hvf, @@ -773,6 +776,10 @@ static void aarch64_host_initfn(Object *obj) ARMCPU *cpu = ARM_CPU(obj); hvf_arm_set_cpu_features_from_host(cpu); aarch64_add_pauth_properties(obj); +#elif defined(CONFIG_WHPX) + ARMCPU *cpu = ARM_CPU(obj); + whpx_arm_set_cpu_features_from_host(cpu); + aarch64_add_pauth_properties(obj); #else g_assert_not_reached(); #endif @@ -780,8 +787,8 @@ static void aarch64_host_initfn(Object *obj) static void aarch64_max_initfn(Object *obj) { - if (kvm_enabled() || hvf_enabled()) { - /* With KVM or HVF, '-cpu max' is identical to '-cpu host' */ + if (hwaccel_enabled()) { + /* When hardware acceleration enabled, '-cpu max' is identical to '-cpu host' */ aarch64_host_initfn(obj); return; } @@ -800,7 +807,7 @@ static const ARMCPUInfo aarch64_cpus[] = { { .name = "cortex-a57", .initfn = aarch64_a57_initfn }, { .name = "cortex-a53", .initfn = aarch64_a53_initfn }, { .name = "max", .initfn = aarch64_max_initfn }, -#if defined(CONFIG_KVM) || defined(CONFIG_HVF) +#if defined(CONFIG_KVM) || defined(CONFIG_HVF) || defined(CONFIG_WHPX) { .name = "host", .initfn = aarch64_host_initfn }, #endif }; diff --git a/target/arm/whpx/whpx-all.c b/target/arm/whpx/whpx-all.c index 19513b50a3..680954f4b5 100644 --- a/target/arm/whpx/whpx-all.c +++ b/target/arm/whpx/whpx-all.c @@ -41,6 +41,17 @@ #include #include +#include + +typedef struct ARMHostCPUFeatures { + ARMISARegisters isar; + uint64_t features; + uint64_t midr; + uint32_t reset_sctlr; + const char *dtb_compatible; +} ARMHostCPUFeatures; + +static ARMHostCPUFeatures arm_host_cpu_features; struct whpx_reg_match { WHV_REGISTER_NAME reg; @@ -695,6 +706,99 @@ static void clamp_id_aa64mmfr0_parange_to_ipa_size(ARMISARegisters *isar) SET_IDREG(isar, ID_AA64MMFR0, id_aa64mmfr0); } +static uint64_t whpx_read_midr(void) +{ + HKEY key; + uint64_t midr_el1; + DWORD size = sizeof(midr_el1); + const char *path = "Hardware\\Description\\System\\CentralProcessor\\0\\"; + assert(!RegOpenKeyExA(HKEY_LOCAL_MACHINE, path, 0, KEY_READ, &key)); + assert(!RegGetValueA(key, NULL, "CP 4000", RRF_RT_REG_QWORD, NULL, &midr_el1, &size)); + RegCloseKey(key); + return midr_el1; +} + +static bool whpx_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) +{ + const struct isar_regs { + WHV_REGISTER_NAME reg; + uint64_t *val; + } regs[] = { + { WHvArm64RegisterIdAa64Pfr0El1, &ahcf->isar.idregs[ID_AA64PFR0_EL1_IDX] }, + { WHvArm64RegisterIdAa64Pfr1El1, &ahcf->isar.idregs[ID_AA64PFR1_EL1_IDX] }, + { WHvArm64RegisterIdAa64Dfr0El1, &ahcf->isar.idregs[ID_AA64DFR0_EL1_IDX] }, + { WHvArm64RegisterIdAa64Dfr1El1 , &ahcf->isar.idregs[ID_AA64DFR1_EL1_IDX] }, + { WHvArm64RegisterIdAa64Isar0El1, &ahcf->isar.idregs[ID_AA64ISAR0_EL1_IDX] }, + { WHvArm64RegisterIdAa64Isar1El1, &ahcf->isar.idregs[ID_AA64ISAR1_EL1_IDX] }, + { WHvArm64RegisterIdAa64Isar2El1, &ahcf->isar.idregs[ID_AA64ISAR2_EL1_IDX] }, + { WHvArm64RegisterIdAa64Mmfr0El1, &ahcf->isar.idregs[ID_AA64MMFR0_EL1_IDX] }, + { WHvArm64RegisterIdAa64Mmfr1El1, &ahcf->isar.idregs[ID_AA64MMFR1_EL1_IDX] }, + { WHvArm64RegisterIdAa64Mmfr2El1, &ahcf->isar.idregs[ID_AA64MMFR2_EL1_IDX] }, + { WHvArm64RegisterIdAa64Mmfr3El1, &ahcf->isar.idregs[ID_AA64MMFR2_EL1_IDX] } + }; + + int i; + WHV_REGISTER_VALUE val; + + ahcf->dtb_compatible = "arm,armv8"; + ahcf->features = (1ULL << ARM_FEATURE_V8) | + (1ULL << ARM_FEATURE_NEON) | + (1ULL << ARM_FEATURE_AARCH64) | + (1ULL << ARM_FEATURE_PMU) | + (1ULL << ARM_FEATURE_GENERIC_TIMER); + + for (i = 0; i < ARRAY_SIZE(regs); i++) { + clean_whv_register_value(&val); + whpx_get_global_reg(regs[i].reg, &val); + *regs[i].val = val.Reg64; + } + + /* + * MIDR_EL1 is not a global register on WHPX + * As such, read the CPU0 from the registry to get a consistent value. + * Otherwise, on heterogenous systems, you'll get variance between CPUs. + */ + ahcf->midr = whpx_read_midr(); + + clamp_id_aa64mmfr0_parange_to_ipa_size(&ahcf->isar); + + /* + * Disable SVE, which is not supported by QEMU whpx yet. + * Work needed for SVE support: + * - SVE state save/restore + * - any potentially needed VL management + * Also disable SME at the same time. (not currently supported by Hyper-V) + */ + SET_IDREG(&ahcf->isar, ID_AA64PFR0, + GET_IDREG(&ahcf->isar, ID_AA64PFR0) & ~R_ID_AA64PFR0_SVE_MASK); + + SET_IDREG(&ahcf->isar, ID_AA64PFR1, + GET_IDREG(&ahcf->isar, ID_AA64PFR1) & ~R_ID_AA64PFR1_SME_MASK); + + return true; +} + +void whpx_arm_set_cpu_features_from_host(ARMCPU *cpu) +{ + if (!arm_host_cpu_features.dtb_compatible) { + if (!whpx_enabled() || + !whpx_arm_get_host_cpu_features(&arm_host_cpu_features)) { + /* + * We can't report this error yet, so flag that we need to + * in arm_cpu_realizefn(). + */ + cpu->host_cpu_probe_failed = true; + return; + } + } + + cpu->dtb_compatible = arm_host_cpu_features.dtb_compatible; + cpu->isar = arm_host_cpu_features.isar; + cpu->env.features = arm_host_cpu_features.features; + cpu->midr = arm_host_cpu_features.midr; + cpu->reset_sctlr = arm_host_cpu_features.reset_sctlr; +} + int whpx_init_vcpu(CPUState *cpu) { HRESULT hr; diff --git a/target/arm/whpx_arm.h b/target/arm/whpx_arm.h index de7406b66f..df65fd753c 100644 --- a/target/arm/whpx_arm.h +++ b/target/arm/whpx_arm.h @@ -12,5 +12,6 @@ #include "target/arm/cpu-qom.h" uint32_t whpx_arm_get_ipa_bit_size(void); +void whpx_arm_set_cpu_features_from_host(ARMCPU *cpu); #endif -- 2.50.1 (Apple Git-155)