[RFC PATCH v2 00/18] iommu/riscv: Add irqbypass support

Andrew Jones
2025-09-20T20:38:53Z

Changelog
---------
This is v2 of the RFC for adding interrupt remapping support to the
RISC-V IOMMU driver along with support for KVM in order to apply it
to irqbypass. v1 of the series was discussed here[1] where a couple
large design flaws were pointed out. Those, along with a v1 TODO of
referencing counting MSI PTEs in order to track when they may be
unmapped, have been addressed in v2. Additionally, v2 is based on
msi-lib, which didn't exist at the time of the v1 posting, and on
the recent KVM irqbypass rework.

Description
-----------
Platforms with MSI support (IMSICs) and implementations of the RISC-V
IOMMU with an MSI table can control device MSI delivery, including
directly delivering MSIs of devices assigned to guests to VCPUs. This
series enables that control and enables IOMMU_DMA in order to use
paging IOMMU domains by default. When the IOMMU doesn't support an MSI
table (it's an optional IOMMU capability) then paging domains are still
used, but the system does not have isolated MSIs. For direct delivery
to VCPUs an MSI table is required and thanks to KVM+VFIO it's possible
to determine when and how to map guest IMSIC addresses to host guest
interrupt files. The RISC-V IOMMU and AIA also support MRIFs (memory-
resident interrupt files), but support for those will be posted as a
follow-on to this series. Also, additional work will be done in order
to take advantage of the RISC-V IOMMU's second stage of paging. At
this time, the series just uses the first stage which allows testing
with unmodified KVM userspace and VFIO.

The patches are organized as follows:
1-4: Create an irq domain and some function stubs for an initial
interrupt remapping support skeleton
5-9: Add MSI table management to enable host interrupt remapping
and enable IOMMU_DMA
10-13: Add IOMMU driver support for directly delivering MSIs to VCPUs
14-17: Add KVM support for directly delivering MSIs to VCPUs

The last patch is a workaround for a KVM bug not introduced by this series
which is needed to enable testing of the series -- I still need to debug
and fix that properly.

There series is also available here[2].

Based on commit 39879e3a4106.

[1] https://lore.kernel.org/all/20241114161845.502027-17-ajones@ventanamicro.com/
[2] https://github.com/jones-drew/linux/commits/riscv/iommu-irqbypass-rfc-v2/

Andrew Jones (13):
genirq/msi: Provide DOMAIN_BUS_MSI_REMAP
iommu/riscv: Move struct riscv_iommu_domain and info to iommu.h
iommu/riscv: Add IRQ domain for interrupt remapping
iommu/riscv: Prepare to use MSI table
iommu/riscv: Implement MSI table management functions
iommu/riscv: Export phys_to_ppn and ppn_to_phys
iommu/riscv: Use MSI table to enable IMSIC access
RISC-V: Define irqbypass vcpu_info
iommu/riscv: Maintain each irq msitbl index with chip data
iommu/riscv: Add guest file irqbypass support
RISC-V: KVM: Add guest file irqbypass support
RISC-V: defconfig: Add VFIO modules
DO NOT UPSTREAM: RISC-V: KVM: Workaround kvm_riscv_gstage_ioremap()
bug

Tomasz Jeznach (4):
iommu/dma: enable IOMMU_DMA for RISC-V
iommu/riscv: report iommu capabilities
RISC-V: KVM: Enable KVM_VFIO interfaces on RISC-V arch
vfio: enable IOMMU_TYPE1 for RISC-V

Zong Li (1):
iommu/riscv: Use data structure instead of individual values

arch/riscv/configs/defconfig | 2 +
arch/riscv/include/asm/irq.h | 9 +
arch/riscv/kvm/Kconfig | 3 +
arch/riscv/kvm/aia_imsic.c | 143 ++++++-
arch/riscv/kvm/mmu.c | 2 +-
arch/riscv/kvm/vm.c | 31 ++
drivers/iommu/Kconfig | 2 +-
drivers/iommu/riscv/Makefile | 2 +-
drivers/iommu/riscv/iommu-bits.h | 11 +
drivers/iommu/riscv/iommu-ir.c | 698 +++++++++++++++++++++++++++++++
drivers/iommu/riscv/iommu.c | 158 +++----
drivers/iommu/riscv/iommu.h | 75 ++++
drivers/irqchip/irq-msi-lib.c | 8 +-
drivers/vfio/Kconfig | 2 +-
include/linux/irqdomain_defs.h | 1 +
15 files changed, 1063 insertions(+), 84 deletions(-)
create mode 100644 drivers/iommu/riscv/iommu-ir.c

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2.49.0