From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5BABD3081B7; Sun, 9 Nov 2025 17:16:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762708593; cv=none; b=hVeJ8cpuLKE0d6UUvyPzHoi1yUl/Tt41ZHLZt4KbccbFOQHHwkMrEzGAzB4W8vfdyWr0tz9hqL92KHQTBgvWdNd8o6/8ZACrIMwSqyKyuCtJbc8JshD8crVXFN/QMly0RL7uIJYXpH31hevBURCZjoBcNN7X9Hvu/W0b4JnGhew= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762708593; c=relaxed/simple; bh=D6ThXSRZO2uuFBNvwNHEMq61UAk/PzFpLpciFk2Nw+A=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ngQ9SRRf9IopBiOwAQ5Qfo0LLt6jDIEbhjRerLMA/rD3zZc8wkRYe6jXp2FpZL+7U+mS87EFpeXI6t+ZtNCyEoneT9U/KIqGhDY3A6wC8S3kpsMQWFMsyJ1m9LgnMOYxpYd+XoElDtx/S5y/A+jaz4MoSb5qtGpyi01OqxBiQr4= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=HV3D1/Z/; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="HV3D1/Z/" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 98E17C19424; Sun, 9 Nov 2025 17:16:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1762708592; bh=D6ThXSRZO2uuFBNvwNHEMq61UAk/PzFpLpciFk2Nw+A=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=HV3D1/Z/kC26IyvLDUVtnV0gH6Ix9wCUTNvgJhIqWEIcmk899/kXXDzP/m+vid1Vb akyifkI47eW756Il1IpG10BcXyLoHXDVR3ZyPKZs8Vks6dhu6PCT56PNrJBZqlg4sK V+DaCBbXnJvKpzmAA9PZcpuKg9FKJUXCSu83hripdMW0OMOrMG/nfevAGre5kg2Bvn cw775gOjzaktH7a399SMtu41vgMDvd8yBZiJMszTLoVvRHhVCHXKNYPD4ce5PXk9Bx yeQ6/QD6Wn6mExVR0sfWtkpI9uylrk3VNhvA18AnBGUzaz3p1SArF/Cav0PRrlZbMv smDU9Qu/lp6QA== Received: from sofa.misterjones.org ([185.219.108.64] helo=valley-girl.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1vI91i-00000003exw-2Lia; Sun, 09 Nov 2025 17:16:30 +0000 From: Marc Zyngier To: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org Cc: Joey Gouly , Suzuki K Poulose , Oliver Upton , Zenghui Yu , Christoffer Dall , Volodymyr Babchuk , Yao Yuan Subject: [PATCH v2 10/45] KVM: arm64: GICv3: Preserve EOIcount on exit Date: Sun, 9 Nov 2025 17:15:44 +0000 Message-ID: <20251109171619.1507205-11-maz@kernel.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251109171619.1507205-1-maz@kernel.org> References: <20251109171619.1507205-1-maz@kernel.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, joey.gouly@arm.com, suzuki.poulose@arm.com, oupton@kernel.org, yuzenghui@huawei.com, christoffer.dall@arm.com, Volodymyr_Babchuk@epam.com, yaoyuan@linux.alibaba.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false EOIcount is how the virtual CPU interface signals that the guest is deactivating interrupts outside of the LRs when EOImode==0. We therefore need to preserve that information so that we can find out what actually needs deactivating. Signed-off-by: Marc Zyngier --- arch/arm64/kvm/hyp/vgic-v3-sr.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/kvm/hyp/vgic-v3-sr.c b/arch/arm64/kvm/hyp/vgic-v3-sr.c index 00ad89d71bb3f..aa04cc9cdc1ab 100644 --- a/arch/arm64/kvm/hyp/vgic-v3-sr.c +++ b/arch/arm64/kvm/hyp/vgic-v3-sr.c @@ -225,6 +225,12 @@ void __vgic_v3_save_state(struct vgic_v3_cpu_if *cpu_if) elrsr = read_gicreg(ICH_ELRSR_EL2); + if (cpu_if->vgic_hcr & ICH_HCR_EL2_LRENPIE) { + u64 val = read_gicreg(ICH_HCR_EL2); + cpu_if->vgic_hcr &= ~ICH_HCR_EL2_EOIcount; + cpu_if->vgic_hcr |= val & ICH_HCR_EL2_EOIcount; + } + write_gicreg(compute_ich_hcr(cpu_if) & ~ICH_HCR_EL2_En, ICH_HCR_EL2); for (i = 0; i < used_lrs; i++) { -- 2.47.3