[PATCH v4 00/49] KVM: arm64: Add LR overflow infrastructure (the final one, I swear!)

Marc Zyngier
2025-11-20T17:25:56Z

As $SUBJECT says, I really hope this is the last dance for this
particular series -- I'm done with it! It was supposed to be a 5 patch
job, and we're close to 50. Something went really wrong...

Most of the fixes have now been squashed back into the base patches,
and the only new patch is plugging the deactivation helper into the NV
code, making it more correct.

Special thanks to Fuad for going the extra mile and testing this
series with pKVM.

* From v3 [3]:

- Squashed most of the previous fixes in their original patch

- Plug the L1 LR handling into the deactivation helper

* From v2 [2]:

- Fix no-vgic-v3. Again.

- Fix clearing of trap bits when running an EL1 host

- Fix the NV handling of the MI, forcing the synchronising of LRs
and VMCR early in order to deliver the MI as early as possible

- Clean some leftovers of previous rework

- Force a read-back of ICH_MISR_EL2 when disabling the vgic, making
NV2 suck a bit less

- Extra fixes made it out of the series:

- Fix pKVM's lack of handling of GICv3 traps, and remember the
VM's vgic type

- Don't explode on non-Apple, non-GICv3 VHE HW by checking
ICH_VTR_EL2 when there is none to check

* From v1 [1]:

- Fixed the ICH_HCR_EL2.TDIR detection code to include the Apple
stuff, and to deal with GICv5's legacy mode

- Fixed compilation issue for old toolchains that don't understand
the GICv3 sysreg names

- Allow GICv3 in-LR deactivation even when DIR trapping is enabled

- Dropped the split overflow list, once I convinced myself it wasn't
bringing much to the table

- Turned kvm_vgic_vcpu_enable() into a vgic reset helper

- Remove IPI-ing on GICv3 systems without TDIR

- Fixed the out-of-LR deactivation when dealing with asymmetric SPI
deactivation

- Fixed broken MMIO offset computation

- Added group enable to the GIC selftest library

- Added fixes and improvements to the vgic_irq selftest:

- Fixed definition of spurious interrupt

- Fixed config/enable ordering

- Prevent timer interrupts from being injected from userspace

- Removed limit of 4 interrupts being injected at any given time

- Added an asymmetric SPI deactivation test case

- Added a Group-0 enable test case

- Added a timer interrupt + SPI interrupt test case

- Fixed a couple of spelling mistakes (and added many more, I'm sure)

- Reordered the series slightly

[1] https://lore.kernel.org/r/20251103165517.2960148-1-maz@kernel.org
[2] https://lore.kernel.org/r/20251109171619.1507205-1-maz@kernel.org
[3] https://lore.kernel.org/r/20251117091527.1119213-1-maz@kernel.org

Marc Zyngier (49):
irqchip/gic: Add missing GICH_HCR control bits
irqchip/gic: Expose CPU interface VA to KVM
irqchip/apple-aic: Spit out ICH_MISR_EL2 value on spurious vGIC MI
KVM: arm64: Turn vgic-v3 errata traps into a patched-in constant
KVM: arm64: vgic-v3: Fix GICv3 trapping in protected mode
KVM: arm64: GICv3: Detect and work around the lack of ICV_DIR_EL1
trapping
KVM: arm64: Repack struct vgic_irq fields
KVM: arm64: Add tracking of vgic_irq being present in a LR
KVM: arm64: Add LR overflow handling documentation
KVM: arm64: GICv3: Drop LPI active state when folding LRs
KVM: arm64: GICv3: Preserve EOIcount on exit
KVM: arm64: GICv3: Decouple ICH_HCR_EL2 programming from LRs
KVM: arm64: GICv3: Extract LR folding primitive
KVM: arm64: GICv3: Extract LR computing primitive
KVM: arm64: GICv2: Preserve EOIcount on exit
KVM: arm64: GICv2: Decouple GICH_HCR programming from LRs being loaded
KVM: arm64: GICv2: Extract LR folding primitive
KVM: arm64: GICv2: Extract LR computing primitive
KVM: arm64: Compute vgic state irrespective of the number of
interrupts
KVM: arm64: Eagerly save VMCR on exit
KVM: arm64: Revamp vgic maintenance interrupt configuration
KVM: arm64: Turn kvm_vgic_vcpu_enable() into kvm_vgic_vcpu_reset()
KVM: arm64: Make vgic_target_oracle() globally available
KVM: arm64: Invert ap_list sorting to push active interrupts out
KVM: arm64: Move undeliverable interrupts to the end of ap_list
KVM: arm64: Use MI to detect groups being enabled/disabled
KVM: arm64: GICv3: Handle LR overflow when EOImode==0
KVM: arm64: GICv3: Handle deactivation via ICV_DIR_EL1 traps
KVM: arm64: GICv3: Add GICv2 SGI handling to deactivation primitive
KVM: arm64: GICv3: Set ICH_HCR_EL2.TDIR when interrupts overflow LR
capacity
KVM: arm64: GICv3: Add SPI tracking to handle asymmetric deactivation
KVM: arm64: GICv3: Handle in-LR deactivation when possible
KVM: arm64: GICv3: Avoid broadcast kick on CPUs lacking TDIR
KVM: arm64: GICv3: nv: Resync LRs/VMCR/HCR early for better MI
emulation
KVM: arm64: GICv3: nv: Plug L1 LR sync into deactivation primitive
KVM: arm64: GICv3: Force exit to sync ICH_HCR_EL2.En
KVM: arm64: GICv2: Handle LR overflow when EOImode==0
KVM: arm64: GICv2: Handle deactivation via GICV_DIR traps
KVM: arm64: GICv2: Always trap GICV_DIR register
KVM: arm64: selftests: gic_v3: Add irq group setting helper
KVM: arm64: selftests: gic_v3: Disable Group-0 interrupts by default
KVM: arm64: selftests: vgic_irq: Fix GUEST_ASSERT_IAR_EMPTY() helper
KVM: arm64: selftests: vgic_irq: Change configuration before enabling
interrupt
KVM: arm64: selftests: vgic_irq: Exclude timer-controlled interrupts
KVM: arm64: selftests: vgic_irq: Remove LR-bound limitation
KVM: arm64: selftests: vgic_irq: Perform EOImode==1 deactivation in
ack order
KVM: arm64: selftests: vgic_irq: Add asymmetric SPI deaectivation test
KVM: arm64: selftests: vgic_irq: Add Group-0 enable test
KVM: arm64: selftests: vgic_irq: Add timer deactivation test

arch/arm64/include/asm/kvm_asm.h | 2 +-
arch/arm64/include/asm/kvm_host.h | 1 +
arch/arm64/include/asm/kvm_hyp.h | 3 +-
arch/arm64/include/asm/virt.h | 7 +-
arch/arm64/kernel/cpufeature.c | 52 +++
arch/arm64/kernel/hyp-stub.S | 5 +
arch/arm64/kernel/image-vars.h | 1 +
arch/arm64/kvm/arm.c | 7 +-
arch/arm64/kvm/hyp/nvhe/hyp-main.c | 7 +-
arch/arm64/kvm/hyp/nvhe/pkvm.c | 3 +
arch/arm64/kvm/hyp/nvhe/sys_regs.c | 5 +
arch/arm64/kvm/hyp/vgic-v2-cpuif-proxy.c | 4 +
arch/arm64/kvm/hyp/vgic-v3-sr.c | 96 ++--
arch/arm64/kvm/sys_regs.c | 19 +-
arch/arm64/kvm/vgic/vgic-init.c | 9 +-
arch/arm64/kvm/vgic/vgic-mmio-v2.c | 24 +
arch/arm64/kvm/vgic/vgic-mmio.h | 1 +
arch/arm64/kvm/vgic/vgic-v2.c | 291 +++++++++---
arch/arm64/kvm/vgic/vgic-v3-nested.c | 104 ++---
arch/arm64/kvm/vgic/vgic-v3.c | 426 ++++++++++++++----
arch/arm64/kvm/vgic/vgic-v4.c | 5 +-
arch/arm64/kvm/vgic/vgic.c | 298 +++++++-----
arch/arm64/kvm/vgic/vgic.h | 43 +-
arch/arm64/tools/cpucaps | 1 +
drivers/irqchip/irq-apple-aic.c | 7 +-
drivers/irqchip/irq-gic.c | 3 +
include/kvm/arm_vgic.h | 29 +-
include/linux/irqchip/arm-gic.h | 6 +
include/linux/irqchip/arm-vgic-info.h | 2 +
tools/testing/selftests/kvm/arm64/vgic_irq.c | 285 +++++++++++-
.../testing/selftests/kvm/include/arm64/gic.h | 1 +
tools/testing/selftests/kvm/lib/arm64/gic.c | 6 +
.../selftests/kvm/lib/arm64/gic_private.h | 1 +
.../testing/selftests/kvm/lib/arm64/gic_v3.c | 17 +
34 files changed, 1352 insertions(+), 419 deletions(-)

--
2.47.3