[kvm-unit-tests PATCH 1/4] lib: riscv: Add SBI PMU CSRs and enums

[James Raphael Tiovalen <jamestiotio@gmail.com>]

Add the CSRs and enum values used by the RISC-V SBI PMU extension.

Signed-off-by: James Raphael Tiovalen <jamestiotio@gmail.com>
---
 lib/riscv/asm/csr.h | 31 +++++++++++++++++
 lib/riscv/asm/sbi.h | 82 +++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 113 insertions(+)

diff --git a/lib/riscv/asm/csr.h b/lib/riscv/asm/csr.h
index 6a8e0578..d5b1c7cc 100644
--- a/lib/riscv/asm/csr.h
+++ b/lib/riscv/asm/csr.h
@@ -14,7 +14,38 @@
 #define CSR_STIMECMP		0x14d
 #define CSR_STIMECMPH		0x15d
 #define CSR_SATP		0x180
+#define CSR_CYCLE		0xc00
 #define CSR_TIME		0xc01
+#define CSR_INSTRET		0xc02
+#define CSR_HPMCOUNTER3		0xc03
+#define CSR_HPMCOUNTER4		0xc04
+#define CSR_HPMCOUNTER5		0xc05
+#define CSR_HPMCOUNTER6		0xc06
+#define CSR_HPMCOUNTER7		0xc07
+#define CSR_HPMCOUNTER8		0xc08
+#define CSR_HPMCOUNTER9		0xc09
+#define CSR_HPMCOUNTER10	0xc0a
+#define CSR_HPMCOUNTER11	0xc0b
+#define CSR_HPMCOUNTER12	0xc0c
+#define CSR_HPMCOUNTER13	0xc0d
+#define CSR_HPMCOUNTER14	0xc0e
+#define CSR_HPMCOUNTER15	0xc0f
+#define CSR_HPMCOUNTER16	0xc10
+#define CSR_HPMCOUNTER17	0xc11
+#define CSR_HPMCOUNTER18	0xc12
+#define CSR_HPMCOUNTER19	0xc13
+#define CSR_HPMCOUNTER20	0xc14
+#define CSR_HPMCOUNTER21	0xc15
+#define CSR_HPMCOUNTER22	0xc16
+#define CSR_HPMCOUNTER23	0xc17
+#define CSR_HPMCOUNTER24	0xc18
+#define CSR_HPMCOUNTER25	0xc19
+#define CSR_HPMCOUNTER26	0xc1a
+#define CSR_HPMCOUNTER27	0xc1b
+#define CSR_HPMCOUNTER28	0xc1c
+#define CSR_HPMCOUNTER29	0xc1d
+#define CSR_HPMCOUNTER30	0xc1e
+#define CSR_HPMCOUNTER31	0xc1f
 
 #define SR_SIE			_AC(0x00000002, UL)
 #define SR_SPP			_AC(0x00000100, UL)
diff --git a/lib/riscv/asm/sbi.h b/lib/riscv/asm/sbi.h
index 289a6a24..35dbf508 100644
--- a/lib/riscv/asm/sbi.h
+++ b/lib/riscv/asm/sbi.h
@@ -47,6 +47,7 @@ enum sbi_ext_id {
 	SBI_EXT_IPI = 0x735049,
 	SBI_EXT_HSM = 0x48534d,
 	SBI_EXT_SRST = 0x53525354,
+	SBI_EXT_PMU = 0x504d55,
 	SBI_EXT_DBCN = 0x4442434E,
 	SBI_EXT_SUSP = 0x53555350,
 	SBI_EXT_FWFT = 0x46574654,
@@ -94,6 +95,87 @@ enum sbi_ext_hsm_hart_suspend_type {
 	SBI_EXT_HSM_HART_SUSPEND_NON_RETENTIVE = 0x80000000,
 };
 
+enum sbi_ext_pmu_fid {
+	SBI_EXT_PMU_NUM_COUNTERS = 0,
+	SBI_EXT_PMU_COUNTER_GET_INFO,
+	SBI_EXT_PMU_COUNTER_CONFIG_MATCHING,
+	SBI_EXT_PMU_COUNTER_START,
+	SBI_EXT_PMU_COUNTER_STOP,
+	SBI_EXT_PMU_COUNTER_FW_READ,
+	SBI_EXT_PMU_COUNTER_FW_READ_HI,
+	SBI_EXT_PMU_SNAPSHOT_SET_SHMEM,
+	SBI_EXT_PMU_EVENT_GET_INFO,
+};
+
+enum sbi_ext_pmu_eid_type {
+	SBI_EXT_PMU_EVENT_HW_GENERAL = 0,
+	SBI_EXT_PMU_EVENT_HW_CACHE,
+	SBI_EXT_PMU_EVENT_HW_RAW,
+	SBI_EXT_PMU_EVENT_HW_RAW_V2,
+	SBI_EXT_PMU_EVENT_FW = 15,
+};
+
+enum sbi_ext_pmu_hw_generic_event_code_id {
+	SBI_EXT_PMU_HW_NO_EVENT = 0,
+	SBI_EXT_PMU_HW_CPU_CYCLES,
+	SBI_EXT_PMU_HW_INSTRUCTIONS,
+	SBI_EXT_PMU_HW_CACHE_REFERENCES,
+	SBI_EXT_PMU_HW_CACHE_MISSES,
+	SBI_EXT_PMU_HW_BRANCH_INSTRUCTIONS,
+	SBI_EXT_PMU_HW_BRANCH_MISSES,
+	SBI_EXT_PMU_HW_BUS_CYCLES,
+	SBI_EXT_PMU_HW_STALLED_CYCLES_FRONTEND,
+	SBI_EXT_PMU_HW_STALLED_CYCLES_BACKEND,
+	SBI_EXT_PMU_HW_REF_CPU_CYCLES,
+};
+
+enum sbi_ext_pmu_hw_cache_id {
+	SBI_EXT_PMU_HW_CACHE_L1D = 0,
+	SBI_EXT_PMU_HW_CACHE_L1I,
+	SBI_EXT_PMU_HW_CACHE_LL,
+	SBI_EXT_PMU_HW_CACHE_DTLB,
+	SBI_EXT_PMU_HW_CACHE_ITLB,
+	SBI_EXT_PMU_HW_CACHE_BPU,
+	SBI_EXT_PMU_HW_CACHE_NODE,
+};
+
+enum sbi_ext_pmu_hw_cache_op_id {
+	SBI_EXT_PMU_HW_CACHE_OP_READ = 0,
+	SBI_EXT_PMU_HW_CACHE_OP_WRITE,
+	SBI_EXT_PMU_HW_CACHE_OP_PREFETCH
+};
+
+enum sbi_ext_pmu_hw_cache_op_result_id {
+	SBI_EXT_PMU_HW_CACHE_RESULT_ACCESS = 0,
+	SBI_EXT_PMU_HW_CACHE_RESULT_MISS,
+};
+
+enum sbi_ext_pmu_fw_event_code_id {
+	SBI_EXT_PMU_FW_MISALIGNED_LOAD = 0,
+	SBI_EXT_PMU_FW_MISALIGNED_STORE,
+	SBI_EXT_PMU_FW_ACCESS_LOAD,
+	SBI_EXT_PMU_FW_ACCESS_STORE,
+	SBI_EXT_PMU_FW_ILLEGAL_INSN,
+	SBI_EXT_PMU_FW_SET_TIMER,
+	SBI_EXT_PMU_FW_IPI_SENT,
+	SBI_EXT_PMU_FW_IPI_RECEIVED,
+	SBI_EXT_PMU_FW_FENCE_I_SENT,
+	SBI_EXT_PMU_FW_FENCE_I_RECEIVED,
+	SBI_EXT_PMU_FW_SFENCE_VMA_SENT,
+	SBI_EXT_PMU_FW_SFENCE_VMA_RECEIVED,
+	SBI_EXT_PMU_FW_SFENCE_VMA_ASID_SENT,
+	SBI_EXT_PMU_FW_SFENCE_VMA_ASID_RECEIVED,
+	SBI_EXT_PMU_FW_HFENCE_GVMA_SENT,
+	SBI_EXT_PMU_FW_HFENCE_GVMA_RECEIVED,
+	SBI_EXT_PMU_FW_HFENCE_GVMA_VMID_SENT,
+	SBI_EXT_PMU_FW_HFENCE_GVMA_VMID_RECEIVED,
+	SBI_EXT_PMU_FW_HFENCE_VVMA_SENT,
+	SBI_EXT_PMU_FW_HFENCE_VVMA_RECEIVED,
+	SBI_EXT_PMU_FW_HFENCE_VVMA_ASID_SENT,
+	SBI_EXT_PMU_FW_HFENCE_VVMA_ASID_RECEIVED,
+	SBI_EXT_PMU_FW_PLATFORM = 65535,
+};
+
 enum sbi_ext_dbcn_fid {
 	SBI_EXT_DBCN_CONSOLE_WRITE = 0,
 	SBI_EXT_DBCN_CONSOLE_READ,
-- 
2.43.0