From: Nikunj A Dadhania <nikunj@amd.com>
To: <seanjc@google.com>, <pbonzini@redhat.com>
Cc: <kvm@vger.kernel.org>, <thomas.lendacky@amd.com>,
<santosh.shukla@amd.com>, <bp@alien8.de>,
<joao.m.martins@oracle.com>, <nikunj@amd.com>,
<kai.huang@intel.com>
Subject: [PATCH v5 5/8] x86/cpufeatures: Add Page modification logging
Date: Mon, 5 Jan 2026 06:36:19 +0000 [thread overview]
Message-ID: <20260105063622.894410-6-nikunj@amd.com> (raw)
In-Reply-To: <20260105063622.894410-1-nikunj@amd.com>
Page modification logging(PML) is a hardware feature designed to track
guest modified memory pages. PML enables the hypervisor to identify which
pages in a guest's memory have been changed since the last checkpoint or
during live migration.
The PML feature is advertised via CPUID leaf 0x8000000A ECX[4] bit.
Acked-by: Borislav Petkov (AMD) <bp@alien8.de>
Signed-off-by: Nikunj A Dadhania <nikunj@amd.com>
---
arch/x86/include/asm/cpufeatures.h | 1 +
arch/x86/kernel/cpu/scattered.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index c3b53beb1300..235e4745c6f2 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -228,6 +228,7 @@
#define X86_FEATURE_PVUNLOCK ( 8*32+20) /* PV unlock function */
#define X86_FEATURE_VCPUPREEMPT ( 8*32+21) /* PV vcpu_is_preempted function */
#define X86_FEATURE_TDX_GUEST ( 8*32+22) /* "tdx_guest" Intel Trust Domain Extensions Guest */
+#define X86_FEATURE_PML ( 8*32+23) /* AMD Page Modification logging */
/* Intel-defined CPU features, CPUID level 0x00000007:0 (EBX), word 9 */
#define X86_FEATURE_FSGSBASE ( 9*32+ 0) /* "fsgsbase" RDFSBASE, WRFSBASE, RDGSBASE, WRGSBASE instructions*/
diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c
index 42c7eac0c387..cdda4e72c5e6 100644
--- a/arch/x86/kernel/cpu/scattered.c
+++ b/arch/x86/kernel/cpu/scattered.c
@@ -53,6 +53,7 @@ static const struct cpuid_bit cpuid_bits[] = {
{ X86_FEATURE_PROC_FEEDBACK, CPUID_EDX, 11, 0x80000007, 0 },
{ X86_FEATURE_AMD_FAST_CPPC, CPUID_EDX, 15, 0x80000007, 0 },
{ X86_FEATURE_MBA, CPUID_EBX, 6, 0x80000008, 0 },
+ { X86_FEATURE_PML, CPUID_ECX, 4, 0x8000000a, 0 },
{ X86_FEATURE_X2AVIC_EXT, CPUID_ECX, 6, 0x8000000a, 0 },
{ X86_FEATURE_COHERENCY_SFW_NO, CPUID_EBX, 31, 0x8000001f, 0 },
{ X86_FEATURE_SMBA, CPUID_EBX, 2, 0x80000020, 0 },
--
2.48.1
next prev parent reply other threads:[~2026-01-05 6:37 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-01-05 6:36 [PATCH v5 0/8] KVM: SVM: Add Page Modification Logging (PML) support Nikunj A Dadhania
2026-01-05 6:36 ` [PATCH v5 1/8] KVM: x86: Carve out PML flush routine Nikunj A Dadhania
2026-01-12 10:02 ` Huang, Kai
2026-01-14 13:57 ` Nikunj A. Dadhania
2026-01-05 6:36 ` [PATCH v5 2/8] KVM: x86: Move PML page to common vcpu arch structure Nikunj A Dadhania
2026-01-12 10:07 ` Huang, Kai
2026-01-05 6:36 ` [PATCH v5 3/8] KVM: VMX: Use cpu_dirty_log_size instead of enable_pml for PML checks Nikunj A Dadhania
2026-01-05 6:49 ` Gupta, Pankaj
2026-01-05 6:36 ` [PATCH v5 4/8] KVM: x86: Move nested CPU dirty logging logic to common code Nikunj A Dadhania
2026-01-12 10:08 ` Huang, Kai
2026-01-05 6:36 ` Nikunj A Dadhania [this message]
2026-01-05 6:36 ` [PATCH v5 6/8] KVM: SVM: Use BIT_ULL for 64-bit nested_ctl bit definitions Nikunj A Dadhania
2026-01-05 6:36 ` [PATCH v5 7/8] KVM: SVM: Add Page modification logging support Nikunj A Dadhania
2026-01-12 10:24 ` Huang, Kai
2026-01-14 14:03 ` Nikunj A. Dadhania
2026-01-14 23:10 ` Huang, Kai
2026-01-14 22:48 ` Huang, Kai
2026-01-16 4:12 ` Nikunj A. Dadhania
2026-01-05 6:36 ` [PATCH v5 8/8] selftests: KVM: x86: Add SEV PML dirty logging test Nikunj A Dadhania
2026-01-14 11:36 ` Huang, Kai
2026-01-14 14:27 ` Nikunj A. Dadhania
2026-01-14 22:44 ` Huang, Kai
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