From: Jonathan Cameron <jonathan.cameron@huawei.com>
To: Sascha Bischoff <Sascha.Bischoff@arm.com>
Cc: "linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"kvmarm@lists.linux.dev" <kvmarm@lists.linux.dev>,
"kvm@vger.kernel.org" <kvm@vger.kernel.org>, nd <nd@arm.com>,
"maz@kernel.org" <maz@kernel.org>,
"oliver.upton@linux.dev" <oliver.upton@linux.dev>,
Joey Gouly <Joey.Gouly@arm.com>,
Suzuki Poulose <Suzuki.Poulose@arm.com>,
"yuzenghui@huawei.com" <yuzenghui@huawei.com>,
"peter.maydell@linaro.org" <peter.maydell@linaro.org>,
"lpieralisi@kernel.org" <lpieralisi@kernel.org>,
Timothy Hayes <Timothy.Hayes@arm.com>
Subject: Re: [PATCH v3 02/36] KVM: arm64: gic-v3: Switch vGIC-v3 to use generated ICH_VMCR_EL2
Date: Mon, 12 Jan 2026 14:00:07 +0000 [thread overview]
Message-ID: <20260112140007.00002391@huawei.com> (raw)
In-Reply-To: <20260109170400.1585048-3-sascha.bischoff@arm.com>
On Fri, 9 Jan 2026 17:04:39 +0000
Sascha Bischoff <Sascha.Bischoff@arm.com> wrote:
> From: Sascha Bischoff <Sascha.Bischoff@arm.com>
>
> The VGIC-v3 code relied on hand-written definitions for the
> ICH_VMCR_EL2 register. This register, and the associated fields, is
> now generated as part of the sysreg framework. Move to using the
> generated definitions instead of the hand-written ones.
>
> There are no functional changes as part of this change.
>
> Signed-off-by: Sascha Bischoff <sascha.bischoff@arm.com>
Hi Sascha,
A couple of trivial things inline that you can feel free to ignore.
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
> ---
> arch/arm64/include/asm/sysreg.h | 21 ---------
> arch/arm64/kvm/hyp/vgic-v3-sr.c | 68 ++++++++++------------------
> arch/arm64/kvm/vgic/vgic-v3-nested.c | 8 ++--
> arch/arm64/kvm/vgic/vgic-v3.c | 48 +++++++++-----------
> 4 files changed, 50 insertions(+), 95 deletions(-)
> diff --git a/arch/arm64/kvm/hyp/vgic-v3-sr.c b/arch/arm64/kvm/hyp/vgic-v3-sr.c
> index 0b670a033fd87..ff10fc71fcd5d 100644
> --- a/arch/arm64/kvm/hyp/vgic-v3-sr.c
> +++ b/arch/arm64/kvm/hyp/vgic-v3-sr.c
> @@ -1064,9 +1047,10 @@ static void __vgic_v3_read_ctlr(struct kvm_vcpu *vcpu, u32 vmcr, int rt)
> /* A3V */
> val |= ((vtr >> 21) & 1) << ICC_CTLR_EL1_A3V_SHIFT;
> /* EOImode */
> - val |= ((vmcr & ICH_VMCR_EOIM_MASK) >> ICH_VMCR_EOIM_SHIFT) << ICC_CTLR_EL1_EOImode_SHIFT;
> + val |= FIELD_PREP(ICC_CTLR_EL1_EOImode_MASK,
> + FIELD_GET(ICH_VMCR_EL2_VEOIM, vmcr));
> /* CBPR */
> - val |= (vmcr & ICH_VMCR_CBPR_MASK) >> ICH_VMCR_CBPR_SHIFT;
> + val |= FIELD_GET(ICH_VMCR_EL2_VCBPR, vmcr);
This one makes me a tiny bit nervous because it's not obvious that this
is kind of FIELD_PREP(FIELD_GET()) like the EOIMode above.
Only a tiny bit though, so it's fine as is.
>
> vcpu_set_reg(vcpu, rt, val);
> }
> @@ -1075,15 +1059,11 @@ static void __vgic_v3_write_ctlr(struct kvm_vcpu *vcpu, u32 vmcr, int rt)
> {
> u32 val = vcpu_get_reg(vcpu, rt);
>
> - if (val & ICC_CTLR_EL1_CBPR_MASK)
> - vmcr |= ICH_VMCR_CBPR_MASK;
> - else
> - vmcr &= ~ICH_VMCR_CBPR_MASK;
> + FIELD_MODIFY(ICH_VMCR_EL2_VCBPR, &vmcr,
> + FIELD_GET(ICC_CTLR_EL1_CBPR_MASK, val));
I'm not laughing at all and the _MASK here because that header
only defines the MASK form, even for single bits :)
>
> - if (val & ICC_CTLR_EL1_EOImode_MASK)
> - vmcr |= ICH_VMCR_EOIM_MASK;
> - else
> - vmcr &= ~ICH_VMCR_EOIM_MASK;
> + FIELD_MODIFY(ICH_VMCR_EL2_VEOIM, &vmcr,
> + FIELD_GET(ICC_CTLR_EL1_EOImode_MASK, val));
>
> write_gicreg(vmcr, ICH_VMCR_EL2);
> }
next prev parent reply other threads:[~2026-01-12 14:00 UTC|newest]
Thread overview: 62+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-01-09 17:04 [PATCH v3 00/36] KVM: arm64: Introduce vGIC-v5 with PPI support Sascha Bischoff
2026-01-09 17:04 ` [PATCH v3 01/36] KVM: arm64: Account for RES1 bits in DECLARE_FEAT_MAP() and co Sascha Bischoff
2026-01-09 17:04 ` [PATCH v3 02/36] KVM: arm64: gic-v3: Switch vGIC-v3 to use generated ICH_VMCR_EL2 Sascha Bischoff
2026-01-12 14:00 ` Jonathan Cameron [this message]
2026-01-28 17:26 ` Sascha Bischoff
2026-01-09 17:04 ` [PATCH v3 03/36] arm64/sysreg: Drop ICH_HFGRTR_EL2.ICC_HAPR_EL1 and make RES1 Sascha Bischoff
2026-01-12 14:03 ` Jonathan Cameron
2026-01-09 17:04 ` [PATCH v3 05/36] arm64/sysreg: Add GICR CDNMIA encoding Sascha Bischoff
2026-01-12 14:39 ` Jonathan Cameron
2026-01-09 17:04 ` [PATCH v3 06/36] KVM: arm64: gic: Set vgic_model before initing private IRQs Sascha Bischoff
2026-01-12 14:37 ` Jonathan Cameron
2026-01-09 17:04 ` [PATCH v3 04/36] arm64/sysreg: Add remaining GICv5 ICC_ & ICH_ sysregs for KVM support Sascha Bischoff
2026-01-09 17:04 ` [PATCH v3 08/36] KVM: arm64: gic: Introduce interrupt type helpers Sascha Bischoff
2026-01-12 14:44 ` Jonathan Cameron
2026-01-09 17:04 ` [PATCH v3 07/36] KVM: arm64: gic-v5: Add ARM_VGIC_V5 device to KVM headers Sascha Bischoff
2026-01-12 14:41 ` Jonathan Cameron
2026-01-09 17:04 ` [PATCH v3 09/36] KVM: arm64: gic-v5: Add Arm copyright header Sascha Bischoff
2026-01-12 14:45 ` Jonathan Cameron
2026-01-09 17:04 ` [PATCH v3 12/36] KVM: arm64: gic-v5: Support GICv5 FGTs & FGUs Sascha Bischoff
2026-01-12 14:55 ` Jonathan Cameron
2026-01-09 17:04 ` [PATCH v3 11/36] KVM: arm64: gic-v5: Sanitize ID_AA64PFR2_EL1.GCIE Sascha Bischoff
2026-01-12 14:47 ` Jonathan Cameron
2026-01-09 17:04 ` [PATCH v3 10/36] KVM: arm64: gic-v5: Detect implemented PPIs on boot Sascha Bischoff
2026-01-12 14:52 ` Jonathan Cameron
2026-01-28 17:28 ` Sascha Bischoff
2026-01-09 17:04 ` [PATCH v3 13/36] KVM: arm64: gic-v5: Add emulation for ICC_IAFFIDR_EL1 accesses Sascha Bischoff
2026-01-09 17:04 ` [PATCH v3 14/36] KVM: arm64: gic-v5: Add vgic-v5 save/restore hyp interface Sascha Bischoff
2026-01-09 17:04 ` [PATCH v3 16/36] KVM: arm64: gic-v5: Implement direct injection of PPIs Sascha Bischoff
2026-01-09 17:04 ` [PATCH v3 15/36] KVM: arm64: gic-v5: Implement GICv5 load/put and save/restore Sascha Bischoff
2026-01-12 15:49 ` Jonathan Cameron
2026-01-28 17:31 ` Sascha Bischoff
2026-01-09 17:04 ` [PATCH v3 17/36] KVM: arm64: gic-v5: Finalize GICv5 PPIs and generate mask Sascha Bischoff
2026-01-09 17:04 ` [PATCH v3 18/36] KVM: arm64: gic: Introduce queue_irq_unlock and set_pending_state to irq_ops Sascha Bischoff
2026-01-09 17:04 ` [PATCH v3 20/36] KVM: arm64: gic-v5: Init Private IRQs (PPIs) for GICv5 Sascha Bischoff
2026-01-09 17:04 ` [PATCH v3 19/36] KVM: arm64: gic-v5: Implement PPI interrupt injection Sascha Bischoff
2026-01-12 16:01 ` Jonathan Cameron
2026-01-09 17:04 ` [PATCH v3 22/36] KVM: arm64: gic-v5: Trap and mask guest ICC_PPI_ENABLERx_EL1 writes Sascha Bischoff
2026-01-12 16:16 ` Jonathan Cameron
2026-01-09 17:04 ` [PATCH v3 23/36] KVM: arm64: gic-v5: Support GICv5 interrupts with KVM_IRQ_LINE Sascha Bischoff
2026-01-09 17:04 ` [PATCH v3 21/36] KVM: arm64: gic-v5: Check for pending PPIs Sascha Bischoff
2026-01-12 16:13 ` Jonathan Cameron
2026-01-13 12:16 ` Joey Gouly
2026-01-09 17:04 ` [PATCH v3 26/36] KVM: arm64: gic-v5: Bump arch timer for GICv5 Sascha Bischoff
2026-01-12 16:27 ` Jonathan Cameron
2026-01-09 17:04 ` [PATCH v3 25/36] KVM: arm64: gic-v5: Reset vcpu state Sascha Bischoff
2026-01-09 17:04 ` [PATCH v3 27/36] KVM: arm64: gic-v5: Mandate architected PPI for PMU emulation on GICv5 Sascha Bischoff
2026-01-12 16:28 ` Jonathan Cameron
2026-01-13 12:11 ` Joey Gouly
2026-01-09 17:04 ` [PATCH v3 24/36] KVM: arm64: gic-v5: Create, init vgic_v5 Sascha Bischoff
2026-01-12 16:20 ` Jonathan Cameron
2026-01-09 17:04 ` [PATCH v3 28/36] KVM: arm64: gic: Hide GICv5 for protected guests Sascha Bischoff
2026-01-09 17:04 ` [PATCH v3 30/36] KVM: arm64: gic-v5: Introduce kvm_arm_vgic_v5_ops and register them Sascha Bischoff
2026-01-12 16:29 ` Jonathan Cameron
2026-01-09 17:04 ` [PATCH v3 29/36] KVM: arm64: gic-v5: Hide FEAT_GCIE from NV GICv5 guests Sascha Bischoff
2026-01-09 17:04 ` [PATCH v3 34/36] Documentation: KVM: Introduce documentation for VGICv5 Sascha Bischoff
2026-01-09 17:04 ` [PATCH v3 33/36] KVM: arm64: gic-v5: Probe for GICv5 device Sascha Bischoff
2026-01-09 17:04 ` [PATCH v3 31/36] KVM: arm64: gic-v5: Set ICH_VCTLR_EL2.En on boot Sascha Bischoff
2026-01-09 17:04 ` [PATCH v3 32/36] irqchip/gic-v5: Check if impl is virt capable Sascha Bischoff
2026-01-09 17:04 ` [PATCH v3 35/36] KVM: arm64: selftests: Introduce a minimal GICv5 PPI selftest Sascha Bischoff
2026-01-12 16:38 ` Jonathan Cameron
2026-01-09 17:04 ` [PATCH v3 36/36] KVM: arm64: gic-v5: Communicate userspace-driveable PPIs via a UAPI Sascha Bischoff
2026-01-12 16:42 ` Jonathan Cameron
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