From: Zide Chen <zide.chen@intel.com>
To: qemu-devel@nongnu.org, kvm@vger.kernel.org,
Paolo Bonzini <pbonzini@redhat.com>,
Zhao Liu <zhao1.liu@intel.com>, Peter Xu <peterx@redhat.com>,
Fabiano Rosas <farosas@suse.de>
Cc: Xiaoyao Li <xiaoyao.li@intel.com>,
Dongli Zhang <dongli.zhang@oracle.com>,
Dapeng Mi <dapeng1.mi@linux.intel.com>,
Zide Chen <zide.chen@intel.com>
Subject: [PATCH V2 02/11] target/i386: Don't save/restore PERF_GLOBAL_OVF_CTRL MSR
Date: Wed, 28 Jan 2026 15:09:39 -0800 [thread overview]
Message-ID: <20260128231003.268981-3-zide.chen@intel.com> (raw)
In-Reply-To: <20260128231003.268981-1-zide.chen@intel.com>
From: Dapeng Mi <dapeng1.mi@linux.intel.com>
MSR_CORE_PERF_GLOBAL_OVF_CTRL is a write-only MSR and reads always
return zero.
Saving and restoring this MSR is therefore unnecessary. Replace
VMSTATE_UINT64 with VMSTATE_UNUSED in the VMStateDescription to ignore
env.msr_global_ovf_ctrl during migration. This avoids the need to bump
version_id and does not introduce any migration incompatibility.
Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
Signed-off-by: Zide Chen <zide.chen@intel.com>
---
V2:
- No changes.
target/i386/cpu.h | 1 -
target/i386/kvm/kvm.c | 6 ------
target/i386/machine.c | 4 ++--
3 files changed, 2 insertions(+), 9 deletions(-)
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index f02812bfd19f..f6e9b274e2ff 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -2086,7 +2086,6 @@ typedef struct CPUArchState {
uint64_t msr_fixed_ctr_ctrl;
uint64_t msr_global_ctrl;
uint64_t msr_global_status;
- uint64_t msr_global_ovf_ctrl;
uint64_t msr_fixed_counters[MAX_FIXED_COUNTERS];
uint64_t msr_gp_counters[MAX_GP_COUNTERS];
uint64_t msr_gp_evtsel[MAX_GP_COUNTERS];
diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c
index 7b9b740a8e5a..cffbc90d1c50 100644
--- a/target/i386/kvm/kvm.c
+++ b/target/i386/kvm/kvm.c
@@ -4069,8 +4069,6 @@ static int kvm_put_msrs(X86CPU *cpu, KvmPutState level)
if (has_architectural_pmu_version > 1) {
kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS,
env->msr_global_status);
- kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
- env->msr_global_ovf_ctrl);
/* Now start the PMU. */
kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL,
@@ -4588,7 +4586,6 @@ static int kvm_get_msrs(X86CPU *cpu)
kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, 0);
- kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 0);
}
for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, 0);
@@ -4917,9 +4914,6 @@ static int kvm_get_msrs(X86CPU *cpu)
case MSR_CORE_PERF_GLOBAL_STATUS:
env->msr_global_status = msrs[i].data;
break;
- case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
- env->msr_global_ovf_ctrl = msrs[i].data;
- break;
case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
break;
diff --git a/target/i386/machine.c b/target/i386/machine.c
index c9139612813b..1125c8a64ec5 100644
--- a/target/i386/machine.c
+++ b/target/i386/machine.c
@@ -666,7 +666,7 @@ static bool pmu_enable_needed(void *opaque)
int i;
if (env->msr_fixed_ctr_ctrl || env->msr_global_ctrl ||
- env->msr_global_status || env->msr_global_ovf_ctrl) {
+ env->msr_global_status) {
return true;
}
for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
@@ -692,7 +692,7 @@ static const VMStateDescription vmstate_msr_architectural_pmu = {
VMSTATE_UINT64(env.msr_fixed_ctr_ctrl, X86CPU),
VMSTATE_UINT64(env.msr_global_ctrl, X86CPU),
VMSTATE_UINT64(env.msr_global_status, X86CPU),
- VMSTATE_UINT64(env.msr_global_ovf_ctrl, X86CPU),
+ VMSTATE_UNUSED(sizeof(uint64_t)),
VMSTATE_UINT64_ARRAY(env.msr_fixed_counters, X86CPU, MAX_FIXED_COUNTERS),
VMSTATE_UINT64_ARRAY(env.msr_gp_counters, X86CPU, MAX_GP_COUNTERS),
VMSTATE_UINT64_ARRAY(env.msr_gp_evtsel, X86CPU, MAX_GP_COUNTERS),
--
2.52.0
next prev parent reply other threads:[~2026-01-28 23:17 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-01-28 23:09 [PATCH V2 00/11] target/i386: Misc PMU, PEBS, and MSR fixes and improvements Zide Chen
2026-01-28 23:09 ` [PATCH V2 01/11] target/i386: Disable unsupported BTS for guest Zide Chen
2026-02-10 6:31 ` Mi, Dapeng
2026-02-11 6:14 ` Xiaoyao Li
2026-03-04 18:22 ` Chen, Zide
2026-01-28 23:09 ` Zide Chen [this message]
2026-01-28 23:09 ` [PATCH V2 03/11] target/i386: Gate enable_pmu on kvm_enabled() Zide Chen
2026-01-28 23:09 ` [PATCH V2 04/11] target/i386: Support full-width writes for perf counters Zide Chen
2026-01-28 23:09 ` [PATCH V2 05/11] target/i386: Increase MSR_BUF_SIZE and split KVM_[GET/SET]_MSRS calls Zide Chen
2026-02-10 6:57 ` Mi, Dapeng
2026-02-10 17:23 ` Chen, Zide
2026-01-28 23:09 ` [PATCH V2 06/11] target/i386: Save/Restore DS based PEBS specfic MSRs Zide Chen
2026-01-28 23:09 ` [PATCH V2 07/11] target/i386: Make some PEBS features user-visible Zide Chen
2026-02-10 7:02 ` Mi, Dapeng
2026-01-28 23:09 ` [PATCH V2 08/11] target/i386: Clean up LBR format handling Zide Chen
2026-02-10 7:07 ` Mi, Dapeng
2026-01-28 23:09 ` [PATCH V2 09/11] target/i386: Refactor " Zide Chen
2026-02-10 7:14 ` Mi, Dapeng
2026-01-28 23:09 ` [PATCH V2 10/11] target/i386: Add pebs-fmt CPU option Zide Chen
2026-01-28 23:09 ` [PATCH V2 11/11] target/i386: Disable guest PEBS capability when not enabled Zide Chen
2026-02-10 7:30 ` Mi, Dapeng
2026-02-10 19:05 ` Chen, Zide
2026-02-11 1:20 ` Mi, Dapeng
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