From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E82BA2FF66A; Mon, 2 Feb 2026 18:43:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770057822; cv=none; b=hgGKRQNlZayvvdLu//Ww3KKInsnBEJB+bIi9GMJbSJ2A54lLI4X1w52bVOVg8Nl1BgIv5bWo47ggbabR4cIFFCLnhLlxaMWlSVPyneKOXTn8wdZO86/rkSd8txxloxijIc3nyWoc7rkIVrcxA2uV+IHPb2xkrOtEfv6VYrAFhlg= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770057822; c=relaxed/simple; bh=KZ1ahPlEHxeFJ4AviJujfAO2tDqTEzqQuzbGo/U0J7E=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=AkfhY1yT4UeF//C1Hs7KlsWBIePtNNV8D7z0xaAAVlsbL8l070YSIAKuCaCNHvvO1zRbj2yC+qpDZYdZKGy7EQhoGNBuYiaaZPqxZYEv/3TD6k1q2oLOl0sbxezA6ivDEQCgbh0mJEwG5GM4bHw1SfC4dFkvNgkTMh5zynuvK9U= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=q0FRdpMT; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="q0FRdpMT" Received: by smtp.kernel.org (Postfix) with ESMTPSA id C5106C116C6; Mon, 2 Feb 2026 18:43:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1770057821; bh=KZ1ahPlEHxeFJ4AviJujfAO2tDqTEzqQuzbGo/U0J7E=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=q0FRdpMTCRZOXGEs6XOEpL69drTkw8uRya5t+iFuWMepBHCOgCt/NwmWXeuPONEkw MhVyjT1P7rCs+8Pk/dRDWE3DMWP6COAKci1KVdnliD7pOqgBBm77qmhiHcDKaBFowg p0KoYdfx+38/grFzXjKP6d+BE27QTIF0d4cYA4bhDzozKm5VzUsZxeuopM07nyBNEK zk2Q0nR7YujHUeJpf+EVaYIm7g5ku5s7ZvtJMgPeSYvBUxVQT1DMcV1KB+vbVVbY0T hunx3umq43btIKGb1CbtSpre8bkxkPl9i+1FZx0vdmxdzzrWC4O+ox+9dmY+S1L8cD jSdlUAeyf8QJg== Received: from sofa.misterjones.org ([185.219.108.64] helo=valley-girl.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1vmytf-00000007sAy-3k2H; Mon, 02 Feb 2026 18:43:39 +0000 From: Marc Zyngier To: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org Cc: Joey Gouly , Suzuki K Poulose , Oliver Upton , Zenghui Yu , Fuad Tabba , Will Deacon , Catalin Marinas Subject: [PATCH v2 05/20] KVM: arm64: Extend unified RESx handling to runtime sanitisation Date: Mon, 2 Feb 2026 18:43:14 +0000 Message-ID: <20260202184329.2724080-6-maz@kernel.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260202184329.2724080-1-maz@kernel.org> References: <20260202184329.2724080-1-maz@kernel.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, joey.gouly@arm.com, suzuki.poulose@arm.com, oupton@kernel.org, yuzenghui@huawei.com, tabba@google.com, will@kernel.org, catalin.marinas@arm.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Add a new helper to retrieve the RESx values for a given system register, and use it for the runtime sanitisation. This results in slightly better code generation for a fairly hot path in the hypervisor, and additionally covers all sanitised registers in all conditions, not just the VNCR-based ones. Reviewed-by: Fuad Tabba Signed-off-by: Marc Zyngier --- arch/arm64/include/asm/kvm_host.h | 15 +++++++++++++++ arch/arm64/kvm/emulate-nested.c | 10 +--------- arch/arm64/kvm/nested.c | 13 ++++--------- 3 files changed, 20 insertions(+), 18 deletions(-) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h index 799f494a1349c..20ebc1610ac84 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -635,6 +635,21 @@ struct kvm_sysreg_masks { struct resx mask[NR_SYS_REGS - __SANITISED_REG_START__]; }; +static inline struct resx __kvm_get_sysreg_resx(struct kvm_arch *arch, + enum vcpu_sysreg sr) +{ + struct kvm_sysreg_masks *masks; + + masks = arch->sysreg_masks; + if (likely(masks && + sr >= __SANITISED_REG_START__ && sr < NR_SYS_REGS)) + return masks->mask[sr - __SANITISED_REG_START__]; + + return (struct resx){}; +} + +#define kvm_get_sysreg_resx(k, sr) __kvm_get_sysreg_resx(&(k)->arch, (sr)) + static inline void __kvm_set_sysreg_resx(struct kvm_arch *arch, enum vcpu_sysreg sr, struct resx resx) { diff --git a/arch/arm64/kvm/emulate-nested.c b/arch/arm64/kvm/emulate-nested.c index 774cfbf5b43ba..43334cd2db9e5 100644 --- a/arch/arm64/kvm/emulate-nested.c +++ b/arch/arm64/kvm/emulate-nested.c @@ -2427,15 +2427,7 @@ static enum trap_behaviour compute_trap_behaviour(struct kvm_vcpu *vcpu, static u64 kvm_get_sysreg_res0(struct kvm *kvm, enum vcpu_sysreg sr) { - struct kvm_sysreg_masks *masks; - - /* Only handle the VNCR-backed regs for now */ - if (sr < __VNCR_START__) - return 0; - - masks = kvm->arch.sysreg_masks; - - return masks->mask[sr - __SANITISED_REG_START__].res0; + return kvm_get_sysreg_resx(kvm, sr).res0; } static bool check_fgt_bit(struct kvm_vcpu *vcpu, enum vcpu_sysreg sr, diff --git a/arch/arm64/kvm/nested.c b/arch/arm64/kvm/nested.c index c5a45bc62153e..75a23f1c56d13 100644 --- a/arch/arm64/kvm/nested.c +++ b/arch/arm64/kvm/nested.c @@ -1669,16 +1669,11 @@ u64 limit_nv_id_reg(struct kvm *kvm, u32 reg, u64 val) u64 kvm_vcpu_apply_reg_masks(const struct kvm_vcpu *vcpu, enum vcpu_sysreg sr, u64 v) { - struct kvm_sysreg_masks *masks; - - masks = vcpu->kvm->arch.sysreg_masks; - - if (masks) { - sr -= __SANITISED_REG_START__; + struct resx resx; - v &= ~masks->mask[sr].res0; - v |= masks->mask[sr].res1; - } + resx = kvm_get_sysreg_resx(vcpu->kvm, sr); + v &= ~resx.res0; + v |= resx.res1; return v; } -- 2.47.3