From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-ot1-f73.google.com (mail-ot1-f73.google.com [209.85.210.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CE10C3191D2 for ; Mon, 9 Feb 2026 22:40:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.73 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770676859; cv=none; b=iYkH+5x9b/tFcDoYWOV2YHNP99iGFC1SbcDko3fz+nVSBLpvNa4pMqYeRcRHXbHKjqCLgdmIz0rj6TBGzgoVX9XQ6RI1kAsb6ld26QDSqtQn+GSji0QEChxmj0rhVtJFo7917QTKU2NMo8qDAD99VmZQ0MZxpaeq3lPMoEfu21I= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770676859; c=relaxed/simple; bh=rirnVzGkSFumuowwu7y/h7aq9o6GqwBPfUtAR73WACo=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=VTpInU5hW4Sgzh4jp7s5ApVtVnUlpz16H5hwdiBYQgMclAjkqEFqKZ/02lSjhIC2gTBWcyGBuLHSi5KVCKGKaSFSy/6t7RUN9YBvvPMN29L/9NDz72ivzu6hAeAjPbfSrX7hpx55ehq+cuFomhm2iUAjhycNjMqqDWxVVunx2vw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--coltonlewis.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=mCPag9YC; arc=none smtp.client-ip=209.85.210.73 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--coltonlewis.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="mCPag9YC" Received: by mail-ot1-f73.google.com with SMTP id 46e09a7af769-7d18d6e6541so9927698a34.3 for ; Mon, 09 Feb 2026 14:40:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1770676852; x=1771281652; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=KEehwDOtOjkxJnHY0L2puQVsuBSwId81nFU3636AvNU=; b=mCPag9YCyog4fEiCV8gPDbPstfJLjNdEcsdNVpbQmvSzq0buRwwsvjupg7pSP9TF1M JBilFrfP75nqoRIdhYZEcwpH4y48mKxLAiW8EcJGm13jmwdCUGKukgig0wK6AifVwfbB UxAboUZvRONyfx6Ert0fZNWMPauhSd5TQhX7tRHvRKsH899FLOGJCB+vkair6djRp1MZ 1OoY0G6tLIrqjYmLb7J/lLNUvNqM4Q1ViHvRxMPeRNVkyzDEYlxut/x5QEfK+theSZ7j MFAbK6kxwdPJmg+woUv9k/KEqUejIC2rzM1rggi1ahY7tlSpeOSQC/GZGfqzlA5VGeeX ZG3g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1770676852; x=1771281652; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=KEehwDOtOjkxJnHY0L2puQVsuBSwId81nFU3636AvNU=; b=FnGwRNqIV5MRqSY+OmumEpAvwoE+yo9zn4HGm9Uv/LHFxD7rQsHRHoMbIR7qIOvdrh GdL8w3ghLtIjo65ZHCzOf2kP2vY5b+A89b+mLcRezQZs9ryx7oi8zd3RECsErutAXsTR /p0y89bfZYNSSSCWgTclB/gtfBNJ5LiNXu74NxDLFPzhMR8HwKWkjBzJ0GRppl0pp8uE R/RZoXTA4hkDnLycf9EjmwoaeLQ0xXlm/3zmF+rfhGtsKIPhDByjmOSp7SO6vtlNhn+f 9sY63j69LvZJye7apsAFLafwAWB6l+xOUQzDf9W807jf56OKoJ/dDBh0fcJ2Nza0qKbu p57w== X-Gm-Message-State: AOJu0YwdYU6+DYZLwhInFUE2Ly8GytmAnYh0D8j23DqdlOQOJtyRZ6HN 9d4lefhfXeP4MepgsC+tC1UI228VJMSVyVx5AJOemyQyM2Crx0KjXQqW1wC1vVX4yXRdpGYUylM P/ZqZbPx9LiUuGpIoGMbPHuUCJ3pUdQLD7c3LxFXHXztwspHIQkoxjDJZFdmcppJdOU8eVl1fjV LKQtvnk+iY24Jb8clEvOrSj8lLMH/5kpQPhEaS5ItcZcVxZwwFSS3h+hsd3ok= X-Received: from iou23.prod.google.com ([2002:a05:6602:64d7:b0:954:2480:2d28]) (user=coltonlewis job=prod-delivery.src-stubby-dispatcher) by 2002:a05:6820:1c84:b0:66a:1886:e4c6 with SMTP id 006d021491bc7-672fe0e4e72mr62956eaf.21.1770676851132; Mon, 09 Feb 2026 14:40:51 -0800 (PST) Date: Mon, 9 Feb 2026 22:14:02 +0000 In-Reply-To: <20260209221414.2169465-1-coltonlewis@google.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20260209221414.2169465-1-coltonlewis@google.com> X-Mailer: git-send-email 2.53.0.rc2.204.g2597b5adb4-goog Message-ID: <20260209221414.2169465-8-coltonlewis@google.com> Subject: [PATCH v6 07/19] KVM: arm64: Set up FGT for Partitioned PMU From: Colton Lewis To: kvm@vger.kernel.org Cc: Alexandru Elisei , Paolo Bonzini , Jonathan Corbet , Russell King , Catalin Marinas , Will Deacon , Marc Zyngier , Oliver Upton , Mingwei Zhang , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Mark Rutland , Shuah Khan , Ganapatrao Kulkarni , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-perf-users@vger.kernel.org, linux-kselftest@vger.kernel.org, Colton Lewis Content-Type: text/plain; charset="UTF-8" In order to gain the best performance benefit from partitioning the PMU, utilize fine grain traps (FEAT_FGT and FEAT_FGT2) to avoid trapping common PMU register accesses by the guest to remove that overhead. Untrapped: * PMCR_EL0 * PMUSERENR_EL0 * PMSELR_EL0 * PMCCNTR_EL0 * PMCNTEN_EL0 * PMINTEN_EL1 * PMEVCNTRn_EL0 These are safe to untrap because writing MDCR_EL2.HPMN as this series will do limits the effect of writes to any of these registers to the partition of counters 0..HPMN-1. Reads from these registers will not leak information from between guests as all these registers are context swapped by a later patch in this series. Reads from these registers also do not leak any information about the host's hardware beyond what is promised by PMUv3. Trapped: * PMOVS_EL0 * PMEVTYPERn_EL0 * PMCCFILTR_EL0 * PMICNTR_EL0 * PMICFILTR_EL0 * PMCEIDn_EL0 * PMMIR_EL1 PMOVS remains trapped so KVM can track overflow IRQs that will need to be injected into the guest. PMICNTR and PMIFILTR remain trapped because KVM is not handling them yet. PMEVTYPERn remains trapped so KVM can limit which events guests can count, such as disallowing counting at EL2. PMCCFILTR and PMCIFILTR are special cases of the same. PMCEIDn and PMMIR remain trapped because they can leak information specific to the host hardware implementation. NOTE: This patch temporarily forces kvm_vcpu_pmu_is_partitioned() to be false to prevent partial feature activation for easier debugging. Signed-off-by: Colton Lewis --- arch/arm64/kvm/config.c | 41 ++++++++++++++++++++++++++++++++++--- arch/arm64/kvm/pmu-direct.c | 33 +++++++++++++++++++++++++++++ include/kvm/arm_pmu.h | 23 +++++++++++++++++++++ 3 files changed, 94 insertions(+), 3 deletions(-) diff --git a/arch/arm64/kvm/config.c b/arch/arm64/kvm/config.c index 24bb3f36e9d59..7daba2537601d 100644 --- a/arch/arm64/kvm/config.c +++ b/arch/arm64/kvm/config.c @@ -1489,12 +1489,47 @@ static void __compute_hfgwtr(struct kvm_vcpu *vcpu) *vcpu_fgt(vcpu, HFGWTR_EL2) |= HFGWTR_EL2_TCR_EL1; } +static void __compute_hdfgrtr(struct kvm_vcpu *vcpu) +{ + __compute_fgt(vcpu, HDFGRTR_EL2); + + *vcpu_fgt(vcpu, HDFGRTR_EL2) |= + HDFGRTR_EL2_PMOVS + | HDFGRTR_EL2_PMCCFILTR_EL0 + | HDFGRTR_EL2_PMEVTYPERn_EL0 + | HDFGRTR_EL2_PMCEIDn_EL0 + | HDFGRTR_EL2_PMMIR_EL1; +} + static void __compute_hdfgwtr(struct kvm_vcpu *vcpu) { __compute_fgt(vcpu, HDFGWTR_EL2); if (is_hyp_ctxt(vcpu)) *vcpu_fgt(vcpu, HDFGWTR_EL2) |= HDFGWTR_EL2_MDSCR_EL1; + + *vcpu_fgt(vcpu, HDFGWTR_EL2) |= + HDFGWTR_EL2_PMOVS + | HDFGWTR_EL2_PMCCFILTR_EL0 + | HDFGWTR_EL2_PMEVTYPERn_EL0; +} + +static void __compute_hdfgrtr2(struct kvm_vcpu *vcpu) +{ + __compute_fgt(vcpu, HDFGRTR2_EL2); + + *vcpu_fgt(vcpu, HDFGRTR2_EL2) &= + ~(HDFGRTR2_EL2_nPMICFILTR_EL0 + | HDFGRTR2_EL2_nPMICNTR_EL0); +} + +static void __compute_hdfgwtr2(struct kvm_vcpu *vcpu) +{ + __compute_fgt(vcpu, HDFGWTR2_EL2); + + *vcpu_fgt(vcpu, HDFGWTR2_EL2) &= + ~(HDFGWTR2_EL2_nPMICFILTR_EL0 + | HDFGWTR2_EL2_nPMICNTR_EL0); } void kvm_vcpu_load_fgt(struct kvm_vcpu *vcpu) @@ -1505,7 +1540,7 @@ void kvm_vcpu_load_fgt(struct kvm_vcpu *vcpu) __compute_fgt(vcpu, HFGRTR_EL2); __compute_hfgwtr(vcpu); __compute_fgt(vcpu, HFGITR_EL2); - __compute_fgt(vcpu, HDFGRTR_EL2); + __compute_hdfgrtr(vcpu); __compute_hdfgwtr(vcpu); __compute_fgt(vcpu, HAFGRTR_EL2); @@ -1515,6 +1550,6 @@ void kvm_vcpu_load_fgt(struct kvm_vcpu *vcpu) __compute_fgt(vcpu, HFGRTR2_EL2); __compute_fgt(vcpu, HFGWTR2_EL2); __compute_fgt(vcpu, HFGITR2_EL2); - __compute_fgt(vcpu, HDFGRTR2_EL2); - __compute_fgt(vcpu, HDFGWTR2_EL2); + __compute_hdfgrtr2(vcpu); + __compute_hdfgwtr2(vcpu); } diff --git a/arch/arm64/kvm/pmu-direct.c b/arch/arm64/kvm/pmu-direct.c index 05ac38ec3ea20..275bd4156871e 100644 --- a/arch/arm64/kvm/pmu-direct.c +++ b/arch/arm64/kvm/pmu-direct.c @@ -42,6 +42,39 @@ bool kvm_pmu_is_partitioned(struct arm_pmu *pmu) pmu->max_guest_counters <= *host_data_ptr(nr_event_counters); } +/** + * kvm_vcpu_pmu_is_partitioned() - Determine if given VCPU has a partitioned PMU + * @vcpu: Pointer to kvm_vcpu struct + * + * Determine if given VCPU has a partitioned PMU by extracting that + * field and passing it to :c:func:`kvm_pmu_is_partitioned` + * + * Return: True if the VCPU PMU is partitioned, false otherwise + */ +bool kvm_vcpu_pmu_is_partitioned(struct kvm_vcpu *vcpu) +{ + return kvm_pmu_is_partitioned(vcpu->kvm->arch.arm_pmu) && + false; +} + +/** + * kvm_vcpu_pmu_use_fgt() - Determine if we can use FGT + * @vcpu: Pointer to struct kvm_vcpu + * + * Determine if we can use FGT for direct access to registers. We can + * if capabilities permit the number of guest counters requested. + * + * Return: True if we can use FGT, false otherwise + */ +bool kvm_vcpu_pmu_use_fgt(struct kvm_vcpu *vcpu) +{ + u8 hpmn = vcpu->kvm->arch.nr_pmu_counters; + + return kvm_vcpu_pmu_is_partitioned(vcpu) && + cpus_have_final_cap(ARM64_HAS_FGT) && + (hpmn != 0 || cpus_have_final_cap(ARM64_HAS_HPMN0)); +} + /** * kvm_pmu_host_counter_mask() - Compute bitmask of host-reserved counters * @pmu: Pointer to arm_pmu struct diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h index accfcb79723c8..50983cdbec045 100644 --- a/include/kvm/arm_pmu.h +++ b/include/kvm/arm_pmu.h @@ -98,6 +98,21 @@ u64 kvm_pmu_guest_counter_mask(struct arm_pmu *pmu); void kvm_pmu_host_counters_enable(void); void kvm_pmu_host_counters_disable(void); +#if !defined(__KVM_NVHE_HYPERVISOR__) +bool kvm_vcpu_pmu_is_partitioned(struct kvm_vcpu *vcpu); +bool kvm_vcpu_pmu_use_fgt(struct kvm_vcpu *vcpu); +#else +static inline bool kvm_vcpu_pmu_is_partitioned(struct kvm_vcpu *vcpu) +{ + return false; +} + +static inline bool kvm_vcpu_pmu_use_fgt(struct kvm_vcpu *vcpu) +{ + return false; +} +#endif + /* * Updates the vcpu's view of the pmu events for this cpu. * Must be called before every vcpu run after disabling interrupts, to ensure @@ -137,6 +152,14 @@ static inline u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, { return 0; } +static inline bool kvm_vcpu_pmu_is_partitioned(struct kvm_vcpu *vcpu) +{ + return false; +} +static inline bool kvm_vcpu_pmu_use_fgt(struct kvm_vcpu *vcpu) +{ + return false; +} static inline void kvm_pmu_set_counter_value(struct kvm_vcpu *vcpu, u64 select_idx, u64 val) {} static inline void kvm_pmu_set_counter_value_user(struct kvm_vcpu *vcpu, -- 2.53.0.rc2.204.g2597b5adb4-goog