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client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by BL02EPF0001A0FE.mail.protection.outlook.com (10.167.242.105) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9678.18 via Frontend Transport; Tue, 10 Mar 2026 06:00:37 +0000 Received: from volcano-f23bhost.amd.com (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.17; Tue, 10 Mar 2026 01:00:34 -0500 From: Manali Shukla To: , CC: , , , , , , , , , , Subject: [PATCH v3 1/9] perf/amd/ibs: Fix race condition in IBS Date: Tue, 10 Mar 2026 06:00:13 +0000 Message-ID: <20260310060022.15120-2-manali.shukla@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260310060022.15120-1-manali.shukla@amd.com> References: <20260310060022.15120-1-manali.shukla@amd.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0001A0FE:EE_|CY8PR12MB8339:EE_ X-MS-Office365-Filtering-Correlation-Id: 2fb1e2a2-2c0b-4215-50f0-08de7e6a59c2 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700016|376014|1800799024; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 2ie30cJzjyg7gTTU3n1rvSPEPDQz6F5m4ZNcK+/eoX4r+Jj4x34JF8tvsF75hga7Dk1KsSI/AXfKUmUMgdfnznv453vJ6+kBzt4n6p+6pCmIdQescu6VDkbqw3ckTmApIzhgcPXqnMuHxoqRHXs7AQP/ityt7lI0a0nX3LyYQRJS7R/e1wp+JejEacKwDPv7KEjKvKt83QJYali7oF/Y3lAboP4Xz8UIkFpk/qC0uKr/uL324vmSyawV0HC1x3JPmI7CP0p030/yGxNhxeDwpwe01PiXndyOHBCR+nttw0K+3hjVbbGmhZhKnfYhLHK2ljrGxbbpDIHmT6VoGhrknZGMQHzcDABP+DONljdJkTfmJWUOzKyJoKUrgU9zv+filIvH+klPley8Eyz0GVhBv4EagzS7B+K1gFSxyvmEGOQZ1U/OIHjTL6XWTP9EIZWB X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Mar 2026 06:00:37.0285 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2fb1e2a2-2c0b-4215-50f0-08de7e6a59c2 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A0FE.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB8339 Consider the following scenario, While scheduling out an IBS event from perf's core scheduling path, event_sched_out() disables the IBS event by clearing the IBS enable bit in perf_ibs_disable_event(). However, if a delayed IBS NMI is delivered after the IBS enable bit is cleared, the IBS NMI handler may still observe the valid bit set and incorrectly treat the sample as valid. As a result, it re-enables IBS by setting the enable bit, even though the event has already been scheduled out. This leads to a situation where IBS is re-enabled after being explicitly disabled, which is incorrect. Although this race does not have visible side effects, it violates the expected behavior of the perf subsystem. The race is particularly noticeable when userspace repeatedly disables and re-enables IBS using PERF_EVENT_IOC_DISABLE and PERF_EVENT_IOC_ENABLE ioctls in a loop. Fix this by checking the IBS_STOPPING bit in the IBS NMI handler before re-enabling the IBS event. If the IBS_STOPPING bit is set, it indicates that the event is either disabled or in the process of being disabled, and the NMI handler should not re-enable it. Signed-off-by: Manali Shukla --- arch/x86/events/amd/ibs.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/x86/events/amd/ibs.c b/arch/x86/events/amd/ibs.c index eeb607b84dda..09b56bab510a 100644 --- a/arch/x86/events/amd/ibs.c +++ b/arch/x86/events/amd/ibs.c @@ -1582,7 +1582,8 @@ static int perf_ibs_handle_irq(struct perf_ibs *perf_ibs, struct pt_regs *iregs) } new_config |= period >> 4; - perf_ibs_enable_event(perf_ibs, hwc, new_config); + if (!test_bit(IBS_STOPPING, pcpu->state)) + perf_ibs_enable_event(perf_ibs, hwc, new_config); } perf_event_update_userpage(event); -- 2.43.0