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Thu, 19 Mar 2026 15:29:11 -0400 (EDT) Date: Thu, 19 Mar 2026 13:29:08 -0600 From: Alex Williamson To: David Matlack Cc: Rubin Du , Shuah Khan , kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, alex@shazbot.org Subject: Re: [PATCH v9 2/2] selftests/vfio: Add NVIDIA Falcon driver for DMA testing Message-ID: <20260319132908.662a32bb@shazbot.org> In-Reply-To: References: <20260317214239.124857-1-rubind@nvidia.com> <20260317214239.124857-3-rubind@nvidia.com> X-Mailer: Claws Mail 4.3.1 (GTK 3.24.51; x86_64-pc-linux-gnu) Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit On Thu, 19 Mar 2026 19:04:37 +0000 David Matlack wrote: > On 2026-03-17 02:42 PM, Rubin Du wrote: > > Add a new VFIO PCI driver for NVIDIA GPUs that enables DMA testing > > via the Falcon (Fast Logic Controller) microcontrollers. This driver > > extracts and adapts the DMA test functionality from the NVIDIA > > gpu-admin-tools project and integrates it into the existing VFIO > > selftest framework. > > > > The Falcon is a general-purpose microcontroller present on NVIDIA GPUs > > that can perform DMA operations between system memory and device memory. > > By leveraging Falcon DMA, this driver allows NVIDIA GPUs to be tested > > alongside Intel IOAT and DSA devices using the same selftest infrastructure. > > > > Supported GPUs: > > - Kepler: K520, GTX660, K4000, K80, GT635 > > - Maxwell Gen1: GTX750, GTX745 > > - Maxwell Gen2: M60 > > - Pascal: P100, P4, P40 > > - Volta: V100 > > - Turing: T4 > > - Ampere: A16, A100, A10 > > - Ada: L4, L40S > > - Hopper: H100 > > > > The PMU falcon on Kepler and Maxwell Gen1 GPUs uses legacy FBIF register > > offsets and requires enabling via PMC_ENABLE with the HUB bit set. > > > > Limitations and tradeoffs: > > > > 1. Architecture support: > > Blackwell and newer architectures may require additional work > > due to firmware. > > > > 2. Synchronous DMA operations: > > Each transfer blocks until completion because the reference > > implementation does not expose command queuing - only one > > DMA operation can be in flight at a time. > > Asynchronous DMA will be important for testing Live Update: > > https://lore.kernel.org/kvm/20260129212510.967611-23-dmatlack@google.com/ > > That is why I split memcpy_start() and memcpy_wait() from the beginning. > > Would it be possible to add support for it here even though it is not in > the reference implementation? I'll leave the can-we questions to Rubin, but do you see either the MSI or asynchronous issues as blockers? Currently our driver tests are limited to a very narrow range of Intel server platforms, whereas this is a plug'able endpoint we can install anywhere. I'd think that's sufficiently valuable in expanding the test base to make some compromises. Thanks, Alex