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Sat, 04 Apr 2026 11:14:38 -0700 (PDT) Received: from archlinux.kangaroo-newton.ts.net ([185.213.155.209]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43d1e4e5890sm26047308f8f.31.2026.04.04.11.14.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 04 Apr 2026 11:14:38 -0700 (PDT) From: Christos Longros To: Alex Williamson Cc: Christos Longros , kvm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2] vfio/pci: sanitize bogus INTx interrupt pin values Date: Sat, 4 Apr 2026 20:14:36 +0200 Message-ID: <20260404181436.754390-1-chris.longros@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260401165920.373e7584@shazbot.org> References: <20260328230126.73230-1-chris.longros@gmail.com> <20260401165920.373e7584@shazbot.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Hi Alex, The RTL8852CE reports a valid interrupt pin (INTA = 0x01) under normal operation. The 0xFF only appears after a VFIO bus reset bricks the device -- at that point the entire config space reads 0xFFFFFFFF, not just the pin register. Since the root cause is the device bricking on bus reset, I think the right fix is a PCI quirk rather than the generic bounds check I proposed here. I have a quirk_no_bus_reset patch ready for 10ec:c852 (RTL8852CE) -- I'll send that as a v3 instead. Should I drop this VFIO patch entirely, or is there value in keeping a safety net for the pin register? The PCI spec limits it to 0x00-0x04, so anything outside that range is invalid, but I understand if you'd rather not add checks for scenarios that shouldn't happen with functioning hardware. Christos