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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-488d5396293sm84794825e9.15.2026.04.10.12.54.51 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 10 Apr 2026 12:54:52 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , "Dr. David Alan Gilbert" , Pierrick Bouvier , qemu-riscv@nongnu.org, Markus Armbruster , qemu-s390x@nongnu.org, kvm@vger.kernel.org, qemu-ppc@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu Subject: [PATCH v2 12/27] target/riscv: Register target_get_monitor_def in SysemuCPUOps Date: Fri, 10 Apr 2026 21:53:06 +0200 Message-ID: <20260410195323.17937-13-philmd@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260410195323.17937-1-philmd@linaro.org> References: <20260410195323.17937-1-philmd@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Rename target_get_monitor_def() as riscv_monitor_get_register_legacy() and register it as SysemuCPUOps::monitor_get_register() handler. Signed-off-by: Philippe Mathieu-Daudé --- target/riscv/internals.h | 3 +++ target/riscv/cpu.c | 1 + target/riscv/monitor.c | 4 +++- 3 files changed, 7 insertions(+), 1 deletion(-) diff --git a/target/riscv/internals.h b/target/riscv/internals.h index 35b923c4bf5..7c91f1872b6 100644 --- a/target/riscv/internals.h +++ b/target/riscv/internals.h @@ -233,4 +233,7 @@ static inline int insn_len(uint16_t first_word) return (first_word & 3) == 3 ? 4 : 2; } +int riscv_monitor_get_register_legacy(CPUState *cs, const char *name, + uint64_t *pval); + #endif diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 8ac935ac06e..dbd88fa6655 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -2720,6 +2720,7 @@ static const struct SysemuCPUOps riscv_sysemu_ops = { .get_phys_page_debug = riscv_cpu_get_phys_page_debug, .write_elf64_note = riscv_cpu_write_elf64_note, .write_elf32_note = riscv_cpu_write_elf32_note, + .monitor_get_register = riscv_monitor_get_register_legacy, .legacy_vmsd = &vmstate_riscv_cpu, }; #endif diff --git a/target/riscv/monitor.c b/target/riscv/monitor.c index 3f206b9fca5..1c90c779534 100644 --- a/target/riscv/monitor.c +++ b/target/riscv/monitor.c @@ -26,6 +26,7 @@ #include "monitor/monitor.h" #include "monitor/hmp.h" #include "system/memory.h" +#include "internals.h" #ifdef TARGET_RISCV64 #define PTE_HEADER_FIELDS "vaddr paddr "\ @@ -310,7 +311,8 @@ static bool reg_is_vreg(const char *name) return false; } -int target_get_monitor_def(CPUState *cs, const char *name, uint64_t *pval) +int riscv_monitor_get_register_legacy(CPUState *cs, const char *name, + uint64_t *pval) { CPURISCVState *env = &RISCV_CPU(cs)->env; target_ulong val = 0; -- 2.53.0