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Date: Thu, 23 Apr 2026 18:16:41 +0200
From: Peter Zijlstra <peterz@infradead.org>
To: Sean Christopherson <seanjc@google.com>
Cc: Ingo Molnar <mingo@redhat.com>,
	Arnaldo Carvalho de Melo <acme@kernel.org>,
	Namhyung Kim <namhyung@kernel.org>,
	Thomas Gleixner <tglx@kernel.org>, Borislav Petkov <bp@alien8.de>,
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	Mingwei Zhang <mizhang@google.com>,
	Stephane Eranian <eranian@google.com>,
	Dapeng Mi <dapeng1.mi@linux.intel.com>
Subject: Re: [PATCH v2 0/4] perf/x86: Don't write PEBS_ENABLED on KVM
 transitions
Message-ID: <20260423161641.GA641209@noisy.programming.kicks-ass.net>
References: <20260423150340.463896-1-seanjc@google.com>
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In-Reply-To: <20260423150340.463896-1-seanjc@google.com>

On Thu, Apr 23, 2026 at 08:03:36AM -0700, Sean Christopherson wrote:
> Testing this against our "PEBS_ENABLED is stuck" reproducer is (still) a work
> in-progress (largely because the "reproducer" is currently "throw the kernel in
> a big test pool"), i.e. I don't know if this actually resolves the problems we
> are seeing.  But even if it doesn't fully resolve our woes, it seems like a
> no-brainer improvement, and if we're missing something with respect to "stuck"
> PEBS_ENABLED, it'd be nice to get feedback/input asap.
> 
> Note, if the throttling theory is correct (which is looking unlikely at the
> moment), then there are likely more fixes that need to be done, e.g. for CPUs
> without isolation, and/or if PERF_GLOBAL_CTRL can be modified from NMI context
> too.

Throttle does: pmu->stop() := x86_pmu_stop() -> intel_pmu_disable_event()

Which in turn should:

  x86_pmu_disable_event()
    wrmsrq(config_base, config & ~EN);
  x86_pmu_pebs_disable() := intel_pmu_pebs_disable()
    wrmsr(PEBS_ENABLE, pebs_enabled & ~(1<<idx));

So that's just the counter EN bit and PEBS_ENABLED cleared. However, if
this is from PMI, then the PMI handler should also update GLOBAL_CTRL --
provided it wasn't 0.

See intel_pmu_handle_irq():

  if (pmu_enabled)
  	__intel_pmu_enable_all()
	  wrmsrq(GLOBAL_CTRL, intel_ctrl);