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Mon, 27 Apr 2026 11:14:17 -0700 From: To: , , , , , , , , , , , , , , , , , , CC: , , , , , , , , , "Manish Honap" Subject: [RFC 8/9] hw/arm/smmu-common: Allow pxb-cxl as SMMUv3 primary bus Date: Mon, 27 Apr 2026 23:42:34 +0530 Message-ID: <20260427181235.3003865-9-mhonap@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260427181235.3003865-1-mhonap@nvidia.com> References: <20260427181235.3003865-1-mhonap@nvidia.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0001A0FC:EE_|DM6PR12MB4041:EE_ X-MS-Office365-Filtering-Correlation-Id: c8aa36e9-57e5-4663-6885-08dea488df16 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|7416014|82310400026|36860700016|921020|56012099003|22082099003|18002099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: /ZjmGiA/lXKWndNkD2yNgYekGH1Yfctloq3Jrm/QyWSWBGe9KjJsbDDULFvAf+9cG0jG9W4qpdhwLL/GG7iw+foQbvLpOHvps4tP0Sfz6Q2vEIyQ86Egr6Pu/SIVeckBfA09iYrtqBLaOLfsqLqJWli/hn8OQE++N6JOK6e378VoHIo/fiCrzNHy8m2PYmZP3LxxH68mxCIIYlhMHev8ksrO6MIL+ccjpYWj853Pl3GjOStCRc/sfFvdR7aHF0/9jrV+iS0dEASxfkCi6a3HrlCcTvuLWF8VW/6+za8/qFqBOu/g9uKy7prNsGfGCtjjUBC15vmSg4kkBDNJE5OrcNApfmt4cvjBMPP7TBsU/epVLXpBss+YKlanYVBBii3S0NE0bf+yx3eSMxml8or7Ur14+2NkVxjlrIzD1BCPkaOzkOLsF3VKSSBXX8bYGKEt X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Apr 2026 18:14:49.6680 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c8aa36e9-57e5-4663-6885-08dea488df16 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A0FC.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4041 From: Manish Honap The SMMUv3 primary bus check only accepted pxb-pcie as a valid root. pxb-cxl uses the same PCIe-compatible bus implementation; reject it and CXL devices behind it cannot reach the IOMMU. Extend the check to also accept CXL buses so SMMUv3 translation applies to passthrough CXL devices. Update the comment above the check to mention pxb-cxl alongside pxb-pcie. Signed-off-by: Shameer Kolothum Signed-off-by: Manish Honap --- hw/arm/smmu-common.c | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c index 58c4452b1f..eb52ea1976 100644 --- a/hw/arm/smmu-common.c +++ b/hw/arm/smmu-common.c @@ -963,19 +963,18 @@ static void smmu_base_realize(DeviceState *dev, Error **errp) s->iommu_ops = &smmu_ops; } /* - * We only allow default PCIe Root Complex(pcie.0) or pxb-pcie based extra - * root complexes to be associated with SMMU. + * We only allow the default PCIe root complex (pcie.0) or pxb-pcie / + * pxb-cxl based extra root complexes to be associated with SMMU. */ if (pci_bus_is_express(pci_bus) && pci_bus_is_root(pci_bus) && object_dynamic_cast(OBJECT(pci_bus)->parent, TYPE_PCI_HOST_BRIDGE)) { /* - * This condition matches either the default pcie.0, pxb-pcie, or - * pxb-cxl. For both pxb-pcie and pxb-cxl, parent_dev will be set. - * Currently, we don't allow pxb-cxl as it requires further - * verification. Therefore, make sure this is indeed pxb-pcie. + * pcie.0 has no parent_dev; pxb-pcie and pxb-cxl do. Accept both + * bus types explicitly so other root complexes are still rejected. */ if (pci_bus->parent_dev) { - if (!object_dynamic_cast(OBJECT(pci_bus), TYPE_PXB_PCIE_BUS)) { + if (!object_dynamic_cast(OBJECT(pci_bus), TYPE_PXB_PCIE_BUS) && + !object_dynamic_cast(OBJECT(pci_bus), TYPE_PXB_CXL_BUS)) { goto out_err; } } @@ -988,8 +987,8 @@ static void smmu_base_realize(DeviceState *dev, Error **errp) return; } out_err: - error_setg(errp, "SMMU should be attached to a default PCIe root complex" - "(pcie.0) or a pxb-pcie based root complex"); + error_setg(errp, "SMMU should be attached to a default PCIe root complex " + "(pcie.0), a pxb-pcie, or a pxb-cxl based root complex"); } /* -- 2.25.1