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Bae" To: pbonzini@redhat.com, seanjc@google.com Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, chao.gao@intel.com, chang.seok.bae@intel.com Subject: [PATCH v3 02/20] KVM: SVM: Macrofy 64-bit GPR swapping in __svm_vcpu_run() Date: Tue, 28 Apr 2026 05:00:53 +0000 Message-ID: <20260428050111.39323-3-chang.seok.bae@intel.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260428050111.39323-1-chang.seok.bae@intel.com> References: <20260428050111.39323-1-chang.seok.bae@intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Convert the register save/restore sequences in SVM entry code to macros, following VMX code. Drop the now-redundant register offset defines. No functional change intended. Signed-off-by: Chang S. Bae --- V2 -> V3: New patch --- arch/x86/kvm/svm/vmenter.S | 38 +++----------------------------------- arch/x86/kvm/vmenter.h | 10 ++++++++++ 2 files changed, 13 insertions(+), 35 deletions(-) diff --git a/arch/x86/kvm/svm/vmenter.S b/arch/x86/kvm/svm/vmenter.S index 358236557454..5f3d2400c60a 100644 --- a/arch/x86/kvm/svm/vmenter.S +++ b/arch/x86/kvm/svm/vmenter.S @@ -17,17 +17,6 @@ #define VCPU_RSI (SVM_vcpu_arch_regs + __VCPU_REGS_RSI * WORD_SIZE) #define VCPU_RDI (SVM_vcpu_arch_regs + __VCPU_REGS_RDI * WORD_SIZE) -#ifdef CONFIG_X86_64 -#define VCPU_R8 (SVM_vcpu_arch_regs + __VCPU_REGS_R8 * WORD_SIZE) -#define VCPU_R9 (SVM_vcpu_arch_regs + __VCPU_REGS_R9 * WORD_SIZE) -#define VCPU_R10 (SVM_vcpu_arch_regs + __VCPU_REGS_R10 * WORD_SIZE) -#define VCPU_R11 (SVM_vcpu_arch_regs + __VCPU_REGS_R11 * WORD_SIZE) -#define VCPU_R12 (SVM_vcpu_arch_regs + __VCPU_REGS_R12 * WORD_SIZE) -#define VCPU_R13 (SVM_vcpu_arch_regs + __VCPU_REGS_R13 * WORD_SIZE) -#define VCPU_R14 (SVM_vcpu_arch_regs + __VCPU_REGS_R14 * WORD_SIZE) -#define VCPU_R15 (SVM_vcpu_arch_regs + __VCPU_REGS_R15 * WORD_SIZE) -#endif - #define SVM_vmcb01_pa (SVM_vmcb01 + KVM_VMCB_pa) .section .noinstr.text, "ax" @@ -115,14 +104,7 @@ SYM_FUNC_START(__svm_vcpu_run) mov VCPU_RBP(%_ASM_DI), %_ASM_BP mov VCPU_RSI(%_ASM_DI), %_ASM_SI #ifdef CONFIG_X86_64 - mov VCPU_R8 (%_ASM_DI), %r8 - mov VCPU_R9 (%_ASM_DI), %r9 - mov VCPU_R10(%_ASM_DI), %r10 - mov VCPU_R11(%_ASM_DI), %r11 - mov VCPU_R12(%_ASM_DI), %r12 - mov VCPU_R13(%_ASM_DI), %r13 - mov VCPU_R14(%_ASM_DI), %r14 - mov VCPU_R15(%_ASM_DI), %r15 + SVM_LOAD_REGS %_ASM_DI, 8,9,10,11,12,13,14,15 #endif mov VCPU_RDI(%_ASM_DI), %_ASM_DI @@ -143,14 +125,7 @@ SYM_FUNC_START(__svm_vcpu_run) mov %_ASM_SI, VCPU_RSI(%_ASM_AX) mov %_ASM_DI, VCPU_RDI(%_ASM_AX) #ifdef CONFIG_X86_64 - mov %r8, VCPU_R8 (%_ASM_AX) - mov %r9, VCPU_R9 (%_ASM_AX) - mov %r10, VCPU_R10(%_ASM_AX) - mov %r11, VCPU_R11(%_ASM_AX) - mov %r12, VCPU_R12(%_ASM_AX) - mov %r13, VCPU_R13(%_ASM_AX) - mov %r14, VCPU_R14(%_ASM_AX) - mov %r15, VCPU_R15(%_ASM_AX) + SVM_STORE_REGS %_ASM_AX, 8,9,10,11,12,13,14,15 #endif /* @svm can stay in RDI from now on. */ @@ -200,14 +175,7 @@ SYM_FUNC_START(__svm_vcpu_run) xor %esi, %esi xor %edi, %edi #ifdef CONFIG_X86_64 - xor %r8d, %r8d - xor %r9d, %r9d - xor %r10d, %r10d - xor %r11d, %r11d - xor %r12d, %r12d - xor %r13d, %r13d - xor %r14d, %r14d - xor %r15d, %r15d + CLEAR_REGS 8d,9d,10d,11d,12d,13d,14d,15d #endif /* "Pop" @enter_flags. */ diff --git a/arch/x86/kvm/vmenter.h b/arch/x86/kvm/vmenter.h index 03e4067c188b..11bfc2729c68 100644 --- a/arch/x86/kvm/vmenter.h +++ b/arch/x86/kvm/vmenter.h @@ -96,6 +96,16 @@ mov %r\i, (VMX_vcpu_arch_regs + \i * WORD_SIZE)(\dst) .endr .endm +.macro SVM_LOAD_REGS src:req, regs:vararg + .irp i, \regs + mov (SVM_vcpu_arch_regs + \i * WORD_SIZE)(\src), %r\i + .endr +.endm +.macro SVM_STORE_REGS dst:req, regs:vararg + .irp i, \regs + mov %r\i, (SVM_vcpu_arch_regs + \i * WORD_SIZE)(\dst) + .endr +.endm #endif #endif /* __ASSEMBLER__ */ -- 2.51.0