From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from out30-100.freemail.mail.aliyun.com (out30-100.freemail.mail.aliyun.com [115.124.30.100]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A10453E8C56; Thu, 7 May 2026 11:37:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=115.124.30.100 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778153854; cv=none; b=htKcKyDuAmopjikIEyCuk1FLmLyqKLkS8/ZGC2qL1M0Z6KcukJsDg/f+fpuKJwiGt95rWDUC7FvUJAR94knolIGopj66d+e9yZI7YGtA+XHFDkrE9m8blT3mcz9wG8GqXvZ4iEUPBT9EIyluLWvCs1OmoAdVWP1pW4dI2oLkhYw= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778153854; c=relaxed/simple; bh=pkbLjK68To7SXmDhh10F9ZkF7vWh9NezqZcwWX8xiSU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=DzQ8JPNg0tPy4ZqjXYdOUnIK3Qtvf8vqQIhY3eGMTTM+956O9uuf/0jm/gin03rcpevC2OlOwfR2/L7Ck9fWllKjgaAdJ2Y0RlWPYg7ENiA8iTxWSsgjtNc7/lrYmfAVfKPgt6/7Usds5WOjmn98jIgJd3cuKNwOK5XvRyqZ0/E= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.alibaba.com; spf=pass smtp.mailfrom=linux.alibaba.com; dkim=pass (1024-bit key) header.d=linux.alibaba.com header.i=@linux.alibaba.com header.b=JkS7lnTQ; arc=none smtp.client-ip=115.124.30.100 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.alibaba.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.alibaba.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.alibaba.com header.i=@linux.alibaba.com header.b="JkS7lnTQ" DKIM-Signature:v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1778153850; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=iJ95MOqqUstSXPIf+KA1zXZMnjUDZYM6/cGTcZoBUgk=; b=JkS7lnTQZ79OnGApxQfGqQwK1IhiVA7PkXGfnGWyKgeP9ZofHSkceZ70t/m3LXaGmvPjJmcRkB5aK+XwBh6f3P2gIBD47cBjZr+JNIuKAE6JFwyo7O1/+gcImMlhh6MWWKIWlpAO4lb47cVn/h3/chuSpAKBQ4SfPGMWK9YXYx0= X-Alimail-AntiSpam:AC=PASS;BC=-1|-1;BR=01201311R201e4;CH=green;DM=||false|;DS=||;FP=0|-1|-1|-1|0|-1|-1|-1;HT=maildocker-contentspam033032089153;MF=fangyu.yu@linux.alibaba.com;NM=1;PH=DS;RN=24;SR=0;TI=SMTPD_---0X2UVF2t_1778153845; Received: from localhost.localdomain(mailfrom:fangyu.yu@linux.alibaba.com fp:SMTPD_---0X2UVF2t_1778153845 cluster:ay36) by smtp.aliyun-inc.com; Thu, 07 May 2026 19:37:26 +0800 From: fangyu.yu@linux.alibaba.com To: joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, tjeznach@rivosinc.com, jgg@ziepe.ca, kevin.tian@intel.com, baolu.lu@linux.intel.com, vasant.hegde@amd.com, anup@brainfault.org, atish.patra@linux.dev, skhawaja@google.com, jgg@nvidia.com Cc: guoren@kernel.org, andrew.jones@oss.qualcomm.com, kvm@vger.kernel.org, iommu@lists.linux.dev, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Fangyu Yu Subject: [RFC PATCH v2 10/10] iommu/riscv: Add IOTINVAL.GVMA after updating DDT/PDT entries Date: Thu, 7 May 2026 19:37:06 +0800 Message-Id: <20260507113706.11400-11-fangyu.yu@linux.alibaba.com> X-Mailer: git-send-email 2.39.3 (Apple Git-146) In-Reply-To: <20260507113706.11400-1-fangyu.yu@linux.alibaba.com> References: <20260507113706.11400-1-fangyu.yu@linux.alibaba.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Fangyu Yu Previously, only IOTINVAL.VMA was issued, which is insufficient for second-stage address translation consistency. Signed-off-by: Fangyu Yu --- drivers/iommu/riscv/iommu.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c index b7944149dcfe..44dd268cc3ce 100644 --- a/drivers/iommu/riscv/iommu.c +++ b/drivers/iommu/riscv/iommu.c @@ -1065,12 +1065,15 @@ static void riscv_iommu_iodir_iotinval(struct riscv_iommu_device *iommu, /* * else: IOTINVAL.VMA with GV=1,AV=PSCV=0,and * GSCID=DC.iohgatp.GSCID - * + */ + riscv_iommu_cmd_send(iommu, &cmd); + /* * IOTINVAL.GVMA with GV=1,AV=0,and * GSCID=DC.iohgatp.GSCID - * TODO: For now, the Second-Stage feature have not yet been merged, - * also issue IOTINVAL.GVMA once second-stage support is merged. */ + riscv_iommu_cmd_inval_gvma(&cmd); + riscv_iommu_cmd_inval_set_gscid(&cmd, + FIELD_GET(RISCV_IOMMU_DC_IOHGATP_GSCID, iohgatp)); } riscv_iommu_cmd_send(iommu, &cmd); } -- 2.50.1