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client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by DS2PEPF00003443.mail.protection.outlook.com (10.167.17.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9891.9 via Frontend Transport; Thu, 7 May 2026 15:39:12 +0000 Received: from MIKCARGYRISD1.amd.com (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.17; Thu, 7 May 2026 10:39:11 -0500 From: Costas Argyris To: Sean Christopherson CC: Jim Mattson , Borislav Petkov , "Joerg Roedel" , Tom Lendacky , , Subject: [PATCH] KVM: selftests: Add guest-side test for AMD HWCR.McStatusWrEn Date: Thu, 7 May 2026 16:38:50 +0100 Message-ID: <20260507153850.8214-1-costas.argyris@amd.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF00003443:EE_|SN7PR12MB8027:EE_ X-MS-Office365-Filtering-Correlation-Id: 951e605f-a405-48be-15d2-08deac4ec9e6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|36860700016|82310400026|1800799024|56012099003|18002099003; X-Microsoft-Antispam-Message-Info: eEBR37izYetKloH3xnhBZKB1wov4uDYjK4CKcs8hwsBAWUQeU59y/+f5CFWWVmOdE2f5LNDGyWI1Z3SJGnRUhVY9QhVfUy2TMf2o6Txdp+WJiLSFlwGYpUnpGyVsEc9VEoiOY/K7NNrO/Wd3ZIRJUntdCu6B37SHcnwitP67uMmDkhmLRkYm1fY6OMDjoT8kOMxSpv1nzxa15ONf6RT9kEhVtTk4DV2UOmEyejDK4Rbkx7n6yOVXQa73iupY4Ctij092/AadZh87tjjMIF6NqqmuEZUH5u+nHoT8gmY3l2jwfi5wXRRM9lsEZ7Sj/xyy70H1Q2zZg3KQgz2BoVwMBtzsehzbYoA0YJysWaMrC3SZ8cuaHKqSFYheFQFWuAjTN1mvlpDJ3RED1arxIZblZJJ1MVFn6odbxfOAXK1N7gWjLlbbM6WGAz5ORABvwXDGo+mo74GwWgDVV9fvjSP5GCE4OViMhoH/8x/35//is733HAH0eEEXhB622OWbuBzxEGIvUyVwprf152IPzMg8/qg1aS2RaUTlVYoRDfW8DmDI6iI7qHNRkMewhyG9cJF4AOlQ9AyXMcipgK30tBo4zXEKdsAqMEX4G2rjYypg3Ay+/BRi3MiBFzLCf4NLrgt696uDiRXezZnslch5phsLH/OmiFAzF78dLJ0+bKVZGdIaUtQUd+gQyUwcVdcFsY6Gnb4KelfUqv+iXndpvnIIJcGUzyZSZXhYVUaGbKSKBDI= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(376014)(36860700016)(82310400026)(1800799024)(56012099003)(18002099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: JpCRD9FbomBQv4fILm6Yla1N6nlmPg9pydj1300bKhuWv1PuS30jMvp1jkmFZt5FxXrfPHMZwti0oluEE41zTzT4B/bpq0YRjZyS9EUEI3rmY7/Us7OyQphYh2FOhMOobRpXpQetrWPMMvWz5gXomj3yq6f8rRa0vNNaXd8oZ2JdvhaifS5R3fL7OHXrcOwrvlo8I3RNTYNfce3j5YoPFNUOEbX0aGic3LAvkmcp8HHZBUr/Q/7vzauOa931k8rQ6+BnPxk4owpicE89LMH4rSsPWPQ0u0nCxEG7XJb0ra3UVvwVWfHHmQE71nnnDrtkNqBGeJynUegh1MJ+kZ3oTHWk23QDMYB9+HqbOZpWPbA/sQU6nX1SaPodi5Lc55rjz2OIO6FtD6iOeas+8ssg+9Ln+tZyilFZRu5nJgCg9XXlHYodokf/i9N2gNXtIqEF X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 May 2026 15:39:12.7545 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 951e605f-a405-48be-15d2-08deac4ec9e6 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF00003443.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB8027 The existing hwcr_msr_test exercises MSR_K7_HWCR only via KVM_SET_MSRS, which sets host_initiated=true in KVM. The gate in set_msr_mce() that calls can_set_mci_status() short-circuits when host_initiated=true, so can_set_mci_status() is never reached by the existing test. Add a guest-side test that verifies HWCR.McStatusWrEn (bit 18) correctly gates non-zero writes to MCi_STATUS MSRs. With the bit set, the write must succeed and read back unchanged. With the bit clear, the write must raise #GP and leave the register unmodified. Signed-off-by: Costas Argyris --- .../testing/selftests/kvm/x86/hwcr_msr_test.c | 65 ++++++++++++++++++- 1 file changed, 63 insertions(+), 2 deletions(-) diff --git a/tools/testing/selftests/kvm/x86/hwcr_msr_test.c b/tools/testing/selftests/kvm/x86/hwcr_msr_test.c index 10b1b0ba374e..4e249bffcbb1 100644 --- a/tools/testing/selftests/kvm/x86/hwcr_msr_test.c +++ b/tools/testing/selftests/kvm/x86/hwcr_msr_test.c @@ -6,9 +6,9 @@ #include "test_util.h" #include "kvm_util.h" -#include "vmx.h" +#include "processor.h" -void test_hwcr_bit(struct kvm_vcpu *vcpu, unsigned int bit) +static void test_hwcr_bit(struct kvm_vcpu *vcpu, unsigned int bit) { const uint64_t ignored = BIT_ULL(3) | BIT_ULL(6) | BIT_ULL(8); const uint64_t valid = BIT_ULL(18) | BIT_ULL(24); @@ -30,6 +30,61 @@ void test_hwcr_bit(struct kvm_vcpu *vcpu, unsigned int bit) vcpu_set_msr(vcpu, MSR_K7_HWCR, 0); } +/* + * AMD-specific: test that HWCR.McStatusWrEn (bit 18) gates guest writes to + * MCi_STATUS MSRs. With the bit set, a non-zero write to MC0_STATUS must + * succeed and read back unchanged. With the bit clear, the write must take + * a #GP. + * + * This exercises arch/x86/kvm/x86.c:can_set_mci_status(), which is only + * reachable via the guest WRMSR path (host_initiated=false); test_hwcr_bit() + * uses KVM_SET_MSRS (host_initiated=true) and never triggers it. + */ +static void guest_code(void) +{ + uint8_t vector; + uint64_t val; + + /* McStatusWrEn=1: non-zero write to MCi_STATUS must succeed. */ + wrmsr(MSR_K7_HWCR, BIT_ULL(18)); + wrmsr(MSR_IA32_MC0_STATUS, 1); + val = rdmsr(MSR_IA32_MC0_STATUS); + GUEST_ASSERT_EQ(val, 1); + + /* Clear the status register before disabling the write-enable bit. */ + wrmsr(MSR_IA32_MC0_STATUS, 0); + + /* McStatusWrEn=0: non-zero write to MCi_STATUS must #GP. */ + wrmsr(MSR_K7_HWCR, 0); + vector = wrmsr_safe(MSR_IA32_MC0_STATUS, 1); + GUEST_ASSERT_EQ(vector, GP_VECTOR); + + /* Confirm the failed write left the register at zero. */ + val = rdmsr(MSR_IA32_MC0_STATUS); + GUEST_ASSERT_EQ(val, 0); + + GUEST_DONE(); +} + +static void enter_guest(struct kvm_vcpu *vcpu) +{ + struct ucall uc; + + while (true) { + vcpu_run(vcpu); + TEST_ASSERT_KVM_EXIT_REASON(vcpu, KVM_EXIT_IO); + + switch (get_ucall(vcpu, &uc)) { + case UCALL_DONE: + return; + case UCALL_ABORT: + REPORT_GUEST_ASSERT(uc); + default: + TEST_FAIL("Unexpected ucall %lu", uc.cmd); + } + } +} + int main(int argc, char *argv[]) { struct kvm_vm *vm; @@ -42,4 +97,10 @@ int main(int argc, char *argv[]) test_hwcr_bit(vcpu, bit); kvm_vm_free(vm); + + if (host_cpu_is_amd_compatible) { + vm = vm_create_with_one_vcpu(&vcpu, guest_code); + enter_guest(vcpu); + kvm_vm_free(vm); + } } -- 2.43.0