From: Ewan Hai <ewandevelop@gmail.com>
To: seanjc@google.com, pbonzini@redhat.com, tglx@kernel.org,
mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com,
x86@kernel.org, hpa@zytor.com, kvm@vger.kernel.org,
linux-kernel@vger.kernel.org
Cc: cobechen@zhaoxin.com, tonywwang@zhaoxin.com
Subject: [PATCH v1 3/5] KVM: x86: Expose Zhaoxin RNG2 CPUID feature
Date: Wed, 13 May 2026 20:48:44 +0800 [thread overview]
Message-ID: <20260513124846.1622462-4-ewandevelop@gmail.com> (raw)
In-Reply-To: <20260513124846.1622462-1-ewandevelop@gmail.com>
Advertise the Zhaoxin second-generation hardware RNG to guests via
CPUID 0xC0000001 EDX bits 22 (RNG2) and 23 (RNG2_EN).
RNG2 is exposed by the REP XRNG2 instruction (encoding F3 0F A7 F8),
documented in the Zhaoxin PadLock Instruction Reference, subsection 1.3
("REP XRNG2"). It produces random bytes from two on-die RNG sources
selectable via RAX bits[10:9] and an output mode (raw vs post-processed)
controlled by RDX bits[1:0], providing high-quality entropy intended
for cryptographic operations.
REP XRNG2 is user-mode and available in all CPU modes, with no
associated MSR control. The RNG2 and RNG2_EN bits are redundant by
hardware design (set or cleared together) and both serve purely as
CPUID-level feature-presence reporting flags requiring no KVM
emulation. Both bits are advertised because different software may
probe either one when checking for RNG2 availability.
Signed-off-by: Ewan Hai <ewandevelop@gmail.com>
---
arch/x86/kvm/cpuid.c | 2 ++
arch/x86/kvm/reverse_cpuid.h | 2 ++
2 files changed, 4 insertions(+)
diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
index 8aaa3f20670e..087c41341240 100644
--- a/arch/x86/kvm/cpuid.c
+++ b/arch/x86/kvm/cpuid.c
@@ -1286,6 +1286,8 @@ void kvm_initialize_cpu_caps(void)
F(PHE_EN),
F(PMM),
F(PMM_EN),
+ F(RNG2),
+ F(RNG2_EN),
);
/*
diff --git a/arch/x86/kvm/reverse_cpuid.h b/arch/x86/kvm/reverse_cpuid.h
index a1cd9116ef63..859ba43126d8 100644
--- a/arch/x86/kvm/reverse_cpuid.h
+++ b/arch/x86/kvm/reverse_cpuid.h
@@ -81,6 +81,8 @@
#define X86_FEATURE_SM2_EN KVM_X86_FEATURE(CPUID_C000_0001_EDX, 1)
#define X86_FEATURE_CCS KVM_X86_FEATURE(CPUID_C000_0001_EDX, 4)
#define X86_FEATURE_CCS_EN KVM_X86_FEATURE(CPUID_C000_0001_EDX, 5)
+#define X86_FEATURE_RNG2 KVM_X86_FEATURE(CPUID_C000_0001_EDX, 22)
+#define X86_FEATURE_RNG2_EN KVM_X86_FEATURE(CPUID_C000_0001_EDX, 23)
struct cpuid_reg {
u32 function;
--
2.34.1
next prev parent reply other threads:[~2026-05-13 12:49 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-13 12:48 [PATCH v1 0/5] KVM: x86: Expose Zhaoxin CPUID 0xC0000001 EDX cryptographic features Ewan Hai
2026-05-13 12:48 ` [PATCH v1 1/5] KVM: x86: Expose Zhaoxin SM2 CPUID feature Ewan Hai
2026-05-13 12:48 ` [PATCH v1 2/5] KVM: x86: Expose Zhaoxin CCS (SM3 + SM4) " Ewan Hai
2026-05-13 12:48 ` Ewan Hai [this message]
2026-05-13 12:48 ` [PATCH v1 4/5] KVM: x86: Expose Zhaoxin PHE2 " Ewan Hai
2026-05-13 12:48 ` [PATCH v1 5/5] KVM: x86: Expose Zhaoxin RSA " Ewan Hai
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