From: Sean Christopherson <seanjc@google.com>
To: Paolo Bonzini <pbonzini@redhat.com>
Cc: kvm@vger.kernel.org, Naveen N Rao <naveen@kernel.org>,
Sean Christopherson <seanjc@google.com>
Subject: [kvm-unit-tests PATCH] x86/apic: Verify LVT timer register mode reads back what was written
Date: Thu, 14 May 2026 14:07:08 -0700 [thread overview]
Message-ID: <20260514210708.1627866-1-seanjc@google.com> (raw)
Report a failure (but not a pass, for brevity) if an APIC timer mode change
reads back a different mode than was written, e.g. to verify that LVTT
reads via x2APIC MSR are accelerated by hardware and access the backing
page when APICv/x2AVIC is enabled.
Cc: Naveen N Rao (AMD) <naveen@kernel.org>
Signed-off-by: Sean Christopherson <seanjc@google.com>
---
x86/apic.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/x86/apic.c b/x86/apic.c
index 0a52e9a4..fab15946 100644
--- a/x86/apic.c
+++ b/x86/apic.c
@@ -569,6 +569,11 @@ static inline void apic_change_mode(unsigned long new_mode)
lvtt = apic_read(APIC_LVTT);
apic_write(APIC_LVTT, (lvtt & ~APIC_LVT_TIMER_MASK) | new_mode);
+
+ lvtt = apic_read(APIC_LVTT);
+ if ((lvtt & APIC_LVT_TIMER_MASK) != new_mode)
+ report_fail("LVTT mode '0x%x' doesn't match written mode '0x%lx'",
+ lvtt & APIC_LVT_TIMER_MASK, new_mode);
}
static void test_apic_change_mode(void)
base-commit: 9eb6c57313060d34f7e5b2ac6f90bb5873bbe2ff
--
2.54.0.563.g4f69b47b94-goog
reply other threads:[~2026-05-14 21:07 UTC|newest]
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