From: Alex Williamson <alex.williamson@nvidia.com>
To: sashiko-bot@kernel.org
Cc: sashiko-reviews@lists.linux.dev,
"Josh Hilke" <jrhilke@google.com>,
kvm@vger.kernel.org
Subject: Re: [PATCH v2 03/10] selftests/vfio: igb: Use advanced TX and RX descriptors
Date: Fri, 29 May 2026 14:24:39 -0600 [thread overview]
Message-ID: <20260529142439.5bd03e5f@nvidia.com> (raw)
In-Reply-To: <20260527001444.69A771F000E9@smtp.kernel.org>
On Wed, 27 May 2026 00:14:44 +0000
sashiko-bot@kernel.org wrote:
> Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
> - [Medium] Overwriting IGB_SRRCTL0 clears the BSIZEPACKET field, setting the receive buffer size to 0 bytes and violating the hardware specification.
> --
>
> commit dc2cc67e8a6e2c641907cee5129b78515c56abca
> Author: Alex Williamson <alex.williamson@nvidia.com>
>
> selftests/vfio: igb: Use advanced TX and RX descriptors
>
> This commit updates the igb selftests driver to use advanced descriptors for
> transmit and receive. It configures SRRCTL.DESCTYPE to the advanced
> one-buffer layout for receive and sets up advanced data descriptor fields
> in igb_memcpy_start() for transmit. Legacy CMD macros are removed.
>
> > diff --git a/tools/testing/selftests/vfio/lib/drivers/igb/igb.c b/tools/testing/selftests/vfio/lib/drivers/igb/igb.c
> > index 5bbc6fca75189..c0f9cefb23e59 100644
> > --- a/tools/testing/selftests/vfio/lib/drivers/igb/igb.c
> > +++ b/tools/testing/selftests/vfio/lib/drivers/igb/igb.c
> > @@ -226,6 +226,17 @@ static void igb_init(struct vfio_pci_device *device)
> > igb_write32(igb, IGB_RDLEN0, RING_SIZE * sizeof(struct igb_rx_desc));
> > igb_write32(igb, IGB_RDH0, 0);
> > igb_write32(igb, IGB_RDT0, 0);
> > +
> > + /*
> > + * Select the advanced one-buffer descriptor format. Per 82576
> > + * datasheet section 7.1.5.2: "SRRCTL[n].DESCTYPE must be set to a
> > + * value other than 000b for the 82576 to write back the special
> > + * descriptors." struct igb_rx_desc matches the advanced one-buffer
> > + * writeback layout (section 7.1.5.2), so polling rx.wb.status_error
> > + * requires this format. Section 8.10.2 specifies DESCTYPE[27:25].
> > + */
> > + igb_write32(igb, IGB_SRRCTL0, IGB_SRRCTL_DESCTYPE_ADV_ONEBUF);
>
> [Severity: Medium]
> Does writing directly to IGB_SRRCTL0 unintentionally clear the BSIZEPACKET
> field?
>
> Because this is a direct write rather than a read-modify-write, all other bits
> in the register are cleared to 0, including BSIZEPACKET (bits 6:0).
>
> The Intel 82576 datasheet dictates that BSIZEPACKET sets the receive buffer
> size in 1 KB increments and explicitly forbids setting it to 0. A 0 value
> leaves the hardware with no space configured for DMA, causing it to drop
> incoming packets.
>
> This behavior remains present in subsequent patches in the series, where
> the macro is updated to E1000_SRRCTL(0) but the BSIZEPACKET field remains
> unpopulated.
>
From the spec...
7.1.3.1 Host Buffers
...
The size of the buffer can be set using either the generic RCTL.BSIZE
field, or the per queue SRRCTL[n].BSIZEPACKET field.
The receive buffer size is selected by bit settings in the Receive
Control (RCTL.BSIZE). The register supports buffer sizes of 256, 512,
1024, and 2048 bytes. See section 12.7.1 for details.
If SRRCTL[n].BSIZEPACKET is set to zero for any queue, the buffer
size defined by RCTL.BSIZE is used. Otherwise, the buffer size
defined by SRRCTL[n].BSIZEPACKET is used.
8.10.1 Receive Control Register - RCTL (0x00100; R/W)
Field Bit(s) Initial Value Description ->
BSIZE 17:16 00b
Receive Buffer Size.
BSIZE controls the size of the receive buffers and permits
software to trade-off descriptor performance versus required
storage space. Buffers that are 2048 bytes require only one
descriptor per receive packet maximizing descriptor
efficiency.
00b = 2048 Bytes.
01b = 1024 Bytes.
10b = 512 Bytes.
11b = 256 Bytes.
False positive. Thanks,
Alex
next prev parent reply other threads:[~2026-05-29 20:24 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-26 23:54 [PATCH v2 00/10] selftests/vfio: igb: Add driver for Intel Josh Hilke
2026-05-26 23:54 ` [PATCH v2 01/10] selftests/vfio: igb: Add driver for IGB QEMU device Josh Hilke
2026-05-27 0:32 ` sashiko-bot
2026-05-26 23:54 ` [PATCH v2 02/10] selftests/vfio: igb: Use PHY internal loopback on 82576 Josh Hilke
2026-05-26 23:54 ` [PATCH v2 03/10] selftests/vfio: igb: Use advanced TX and RX descriptors Josh Hilke
2026-05-27 0:14 ` sashiko-bot
2026-05-29 20:24 ` Alex Williamson [this message]
2026-05-26 23:54 ` [PATCH v2 04/10] selftests/vfio: igb: Program MSI-X interrupt routing Josh Hilke
2026-05-27 0:19 ` sashiko-bot
2026-05-29 20:24 ` Alex Williamson
2026-05-26 23:54 ` [PATCH v2 05/10] selftests/vfio: igb: Extend memcpy completion timeout for line-rate hardware Josh Hilke
2026-05-26 23:54 ` [PATCH v2 06/10] selftests/vfio: igb: Disable PCIe completion timeout retries Josh Hilke
2026-05-26 23:54 ` [PATCH v2 07/10] selftests/vfio: Add vfio_pci_irq_reenable() helper Josh Hilke
2026-05-26 23:54 ` [PATCH v2 08/10] selftests/vfio: igb: Factor hardware programming into igb_hw_init() Josh Hilke
2026-05-26 23:54 ` [PATCH v2 09/10] selftests/vfio: igb: Recover after DMA-read faults Josh Hilke
2026-05-26 23:54 ` [PATCH v2 10/10] selftests/vfio: igb: Use offical IGB headers in selftest driver Josh Hilke
2026-05-27 2:40 ` sashiko-bot
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