Re: [PATCH v2 2/7] KVM: riscv: selftests: add Svadu FWFT extension to get-reg-list test

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] Unconditional selftest failure in get-reg-list due to dynamically-omitted registers in the blessed list.
--

commit 6df4c1234104e4c676015802e2b610d953076f46
Author: Inochi Amaoto <inochiama@gmail.com>

KVM: riscv: selftests: add Svadu FWFT extension to get-reg-list test
    
This commit adds the Svadu FWFT extension registers to the get-reg-list
selftest's expected register list.

> diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c b/tools/testing/selftests/kvm/riscv/get-reg-list.c
> index 8d6fdb5d38b89..d88edef77ccfd 100644
> --- a/tools/testing/selftests/kvm/riscv/get-reg-list.c
> +++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c
[ ... ]
> @@ -905,6 +908,9 @@ static __u64 sbi_fwft_regs[] = {
>  	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(pointer_masking.enable),
>  	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(pointer_masking.flags),
>  	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(pointer_masking.value),
> +	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(pte_ad_hw_updating.enable),
> +	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(pte_ad_hw_updating.flags),
> +	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(pte_ad_hw_updating.value),
>  };

[Severity: Medium]
Will this cause an unconditional selftest failure when the SVADU extension
is disabled?

The RISC-V get-reg-list selftest disables all ISA extensions (including SVADU)
by default to ensure a clean baseline. The KVM implementation conditionally
exposes these pte_ad_hw_updating registers only if the SVADU ISA extension is
enabled on the vCPU.

Because the registers are added unconditionally to the expected list here,
and RISC-V does not override check_supported_reg() to conditionally filter
them out, KVM omitting these registers from KVM_GET_REG_LIST will cause the
test framework to fail with a missing registers assertion.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260601084336.2601675-1-inochiama@gmail.com?part=2