From: Yixun Lan <dlan@kernel.org>
To: Guodong Xu <docular.xu@gmail.com>
Cc: Jonathan Corbet <corbet@lwn.net>,
Shuah Khan <skhan@linuxfoundation.org>,
Paul Walmsley <pjw@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Alexandre Ghiti <alex@ghiti.fr>, Zong Li <zong.li@sifive.com>,
Deepak Gupta <debug@rivosinc.com>,
Anup Patel <anup@brainfault.org>,
Atish Patra <atish.patra@linux.dev>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Chen Wang <unicorn_wang@outlook.com>,
Inochi Amaoto <inochiama@gmail.com>,
linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org, kvm@vger.kernel.org,
kvm-riscv@lists.infradead.org,
Paul Walmsley <paul.walmsley@sifive.com>,
Conor Dooley <conor@kernel.org>,
devicetree@vger.kernel.org, spacemit@lists.linux.dev,
sophgo@lists.linux.dev, linux-kselftest@vger.kernel.org,
Palmer Dabbelt <palmer@sifive.com>
Subject: Re: [PATCH v4 10/16] riscv: dts: spacemit: k3: Add Zic64b ISA extension
Date: Mon, 15 Jun 2026 01:20:29 +0000 [thread overview]
Message-ID: <20260615012029-GKA1003249@kernel.org> (raw)
In-Reply-To: <20260611-rva23u64-hwprobe-v2-v4-10-3f01a2449488@gmail.com>
Hi Guodong,
On 16:12 Thu 11 Jun , Guodong Xu wrote:
> The K3 X100 cores have 64-byte cache blocks, already described by their
> cbom/cbop/cboz-block-size of 64, so they implement Zic64b, a mandatory
> RVA23 extension. Declare it in each core's riscv,isa-extensions.
>
> Signed-off-by: Guodong Xu <docular.xu@gmail.com>
Reviewed-by: Yixun Lan <dlan@kernel.org>
> ---
> v4: No change.
> v3: New patch.
> ---
> arch/riscv/boot/dts/spacemit/k3.dtsi | 48 ++++++++++++++++++------------------
> 1 file changed, 24 insertions(+), 24 deletions(-)
>
> diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi
> index 4ac457399b583..b5aa983f0bfa1 100644
> --- a/arch/riscv/boot/dts/spacemit/k3.dtsi
> +++ b/arch/riscv/boot/dts/spacemit/k3.dtsi
> @@ -35,9 +35,9 @@ cpu_0: cpu@0 {
> "svinval", "svnapot", "svpbmt", "za64rs",
> "zawrs", "zba", "zbb", "zbc", "zbs", "zca",
> "zcb", "zcd", "zcmop", "zfa", "zfbfmin",
> - "zfh", "zfhmin", "zicbom", "zicbop", "zicboz",
> - "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr",
> - "zicond", "zicsr", "zifencei", "zihintntl",
> + "zfh", "zfhmin", "zic64b", "zicbom", "zicbop",
> + "zicboz", "ziccamoa", "ziccif", "zicclsm", "ziccrse",
> + "zicntr", "zicond", "zicsr", "zifencei", "zihintntl",
> "zihintpause", "zihpm", "zimop", "zkt", "zvbb",
> "zvbc", "zvfbfmin", "zvfbfwma", "zvfh",
> "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc",
> @@ -76,9 +76,9 @@ cpu_1: cpu@1 {
> "svinval", "svnapot", "svpbmt", "za64rs",
> "zawrs", "zba", "zbb", "zbc", "zbs", "zca",
> "zcb", "zcd", "zcmop", "zfa", "zfbfmin",
> - "zfh", "zfhmin", "zicbom", "zicbop", "zicboz",
> - "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr",
> - "zicond", "zicsr", "zifencei", "zihintntl",
> + "zfh", "zfhmin", "zic64b", "zicbom", "zicbop",
> + "zicboz", "ziccamoa", "ziccif", "zicclsm", "ziccrse",
> + "zicntr", "zicond", "zicsr", "zifencei", "zihintntl",
> "zihintpause", "zihpm", "zimop", "zkt", "zvbb",
> "zvbc", "zvfbfmin", "zvfbfwma", "zvfh",
> "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc",
> @@ -117,9 +117,9 @@ cpu_2: cpu@2 {
> "svinval", "svnapot", "svpbmt", "za64rs",
> "zawrs", "zba", "zbb", "zbc", "zbs", "zca",
> "zcb", "zcd", "zcmop", "zfa", "zfbfmin",
> - "zfh", "zfhmin", "zicbom", "zicbop", "zicboz",
> - "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr",
> - "zicond", "zicsr", "zifencei", "zihintntl",
> + "zfh", "zfhmin", "zic64b", "zicbom", "zicbop",
> + "zicboz", "ziccamoa", "ziccif", "zicclsm", "ziccrse",
> + "zicntr", "zicond", "zicsr", "zifencei", "zihintntl",
> "zihintpause", "zihpm", "zimop", "zkt", "zvbb",
> "zvbc", "zvfbfmin", "zvfbfwma", "zvfh",
> "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc",
> @@ -158,9 +158,9 @@ cpu_3: cpu@3 {
> "svinval", "svnapot", "svpbmt", "za64rs",
> "zawrs", "zba", "zbb", "zbc", "zbs", "zca",
> "zcb", "zcd", "zcmop", "zfa", "zfbfmin",
> - "zfh", "zfhmin", "zicbom", "zicbop", "zicboz",
> - "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr",
> - "zicond", "zicsr", "zifencei", "zihintntl",
> + "zfh", "zfhmin", "zic64b", "zicbom", "zicbop",
> + "zicboz", "ziccamoa", "ziccif", "zicclsm", "ziccrse",
> + "zicntr", "zicond", "zicsr", "zifencei", "zihintntl",
> "zihintpause", "zihpm", "zimop", "zkt", "zvbb",
> "zvbc", "zvfbfmin", "zvfbfwma", "zvfh",
> "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc",
> @@ -199,9 +199,9 @@ cpu_4: cpu@4 {
> "svinval", "svnapot", "svpbmt", "za64rs",
> "zawrs", "zba", "zbb", "zbc", "zbs", "zca",
> "zcb", "zcd", "zcmop", "zfa", "zfbfmin",
> - "zfh", "zfhmin", "zicbom", "zicbop", "zicboz",
> - "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr",
> - "zicond", "zicsr", "zifencei", "zihintntl",
> + "zfh", "zfhmin", "zic64b", "zicbom", "zicbop",
> + "zicboz", "ziccamoa", "ziccif", "zicclsm", "ziccrse",
> + "zicntr", "zicond", "zicsr", "zifencei", "zihintntl",
> "zihintpause", "zihpm", "zimop", "zkt", "zvbb",
> "zvbc", "zvfbfmin", "zvfbfwma", "zvfh",
> "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc",
> @@ -240,9 +240,9 @@ cpu_5: cpu@5 {
> "svinval", "svnapot", "svpbmt", "za64rs",
> "zawrs", "zba", "zbb", "zbc", "zbs", "zca",
> "zcb", "zcd", "zcmop", "zfa", "zfbfmin",
> - "zfh", "zfhmin", "zicbom", "zicbop", "zicboz",
> - "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr",
> - "zicond", "zicsr", "zifencei", "zihintntl",
> + "zfh", "zfhmin", "zic64b", "zicbom", "zicbop",
> + "zicboz", "ziccamoa", "ziccif", "zicclsm", "ziccrse",
> + "zicntr", "zicond", "zicsr", "zifencei", "zihintntl",
> "zihintpause", "zihpm", "zimop", "zkt", "zvbb",
> "zvbc", "zvfbfmin", "zvfbfwma", "zvfh",
> "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc",
> @@ -281,9 +281,9 @@ cpu_6: cpu@6 {
> "svinval", "svnapot", "svpbmt", "za64rs",
> "zawrs", "zba", "zbb", "zbc", "zbs", "zca",
> "zcb", "zcd", "zcmop", "zfa", "zfbfmin",
> - "zfh", "zfhmin", "zicbom", "zicbop", "zicboz",
> - "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr",
> - "zicond", "zicsr", "zifencei", "zihintntl",
> + "zfh", "zfhmin", "zic64b", "zicbom", "zicbop",
> + "zicboz", "ziccamoa", "ziccif", "zicclsm", "ziccrse",
> + "zicntr", "zicond", "zicsr", "zifencei", "zihintntl",
> "zihintpause", "zihpm", "zimop", "zkt", "zvbb",
> "zvbc", "zvfbfmin", "zvfbfwma", "zvfh",
> "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc",
> @@ -322,9 +322,9 @@ cpu_7: cpu@7 {
> "svinval", "svnapot", "svpbmt", "za64rs",
> "zawrs", "zba", "zbb", "zbc", "zbs", "zca",
> "zcb", "zcd", "zcmop", "zfa", "zfbfmin",
> - "zfh", "zfhmin", "zicbom", "zicbop", "zicboz",
> - "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr",
> - "zicond", "zicsr", "zifencei", "zihintntl",
> + "zfh", "zfhmin", "zic64b", "zicbom", "zicbop",
> + "zicboz", "ziccamoa", "ziccif", "zicclsm", "ziccrse",
> + "zicntr", "zicond", "zicsr", "zifencei", "zihintntl",
> "zihintpause", "zihpm", "zimop", "zkt", "zvbb",
> "zvbc", "zvfbfmin", "zvfbfwma", "zvfh",
> "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc",
>
> --
> 2.43.0
>
--
Yixun Lan (dlan)
next prev parent reply other threads:[~2026-06-15 1:20 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-11 20:12 [PATCH v4 00/16] riscv: hwprobe: Expose RVA23U64 base behavior Guodong Xu
2026-06-11 20:12 ` [PATCH v4 01/16] dt-bindings: riscv: sort multi-letter Z extensions alphanumerically Guodong Xu
2026-06-12 8:02 ` Conor Dooley
2026-06-11 20:12 ` [PATCH v4 02/16] riscv: hwprobe.rst: Make indentation consistent Guodong Xu
2026-06-11 20:12 ` [PATCH v4 03/16] riscv: hwprobe.rst: Document EXT_ZICFISS and EXT_ZICFILP Guodong Xu
2026-06-11 20:12 ` [PATCH v4 04/16] riscv: Standardize extension capitalization Guodong Xu
2026-06-11 20:12 ` [PATCH v4 05/16] riscv: Add Zicclsm to cpufeature and hwprobe Guodong Xu
2026-06-12 13:51 ` Jesse Taube
2026-06-11 20:12 ` [PATCH v4 06/16] riscv: Add Ziccamoa, Ziccif, Ziccrse, and Za64rs " Guodong Xu
2026-06-12 8:10 ` Conor Dooley
2026-06-11 20:12 ` [PATCH v4 07/16] riscv: Add B to hwcap " Guodong Xu
2026-06-12 8:12 ` Conor Dooley
2026-06-11 20:12 ` [PATCH v4 08/16] dt-bindings: riscv: Add Zic64b extension description Guodong Xu
2026-06-12 8:23 ` Conor Dooley
2026-06-11 20:12 ` [PATCH v4 09/16] riscv: Add Zic64b to cpufeature and hwprobe Guodong Xu
2026-06-11 20:50 ` Andrew Jones
2026-06-12 8:41 ` Conor Dooley
2026-06-11 20:12 ` [PATCH v4 10/16] riscv: dts: spacemit: k3: Add Zic64b ISA extension Guodong Xu
2026-06-15 1:20 ` Yixun Lan [this message]
2026-06-11 20:12 ` [PATCH v4 11/16] riscv: dts: spacemit: k1: " Guodong Xu
2026-06-11 20:12 ` [PATCH v4 12/16] riscv: dts: sophgo: sg2044: " Guodong Xu
2026-06-11 20:12 ` [PATCH v4 13/16] riscv: Add a getter for user PMLEN support Guodong Xu
2026-06-11 20:12 ` [PATCH v4 14/16] riscv: cpufeature: Introduce ISA bases bitmap and rva23u64 detection Guodong Xu
2026-06-11 20:32 ` sashiko-bot
2026-06-11 20:12 ` [PATCH v4 15/16] riscv: cpu: Output isa bases lines in cpuinfo Guodong Xu
2026-06-11 20:12 ` [PATCH v4 16/16] riscv: hwprobe: Introduce rva23u64 base behavior Guodong Xu
2026-06-11 20:42 ` sashiko-bot
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