From: Aditya Gupta <adityag@linux.ibm.com>
To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org,
"Harsh Prateek Bora" <harshpb@linux.ibm.com>,
"Cédric Le Goater" <clg@redhat.com>,
"Philippe Mathieu-Daudé" <philmd@oss.qualcomm.com>,
"Shivang Upadhyay" <shivangu@linux.ibm.com>
Cc: Sourabh Jain <sourabhjain@linux.ibm.com>,
Hari Bathini <hbathini@linux.ibm.com>,
Nicholas Piggin <npiggin@gmail.com>,
Miles Glenn <milesg@linux.ibm.com>,
Fabiano Rosas <farosas@suse.de>,
Laurent Vivier <lvivier@redhat.com>,
Paolo Bonzini <pbonzini@redhat.com>,
devel@lists.libvirt.org, Misbah Anjum N <misanjum@linux.ibm.com>,
Anushree Mathur <anushree.mathur@linux.ibm.com>,
Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>,
kvm@vger.kernel.org, Gautam Menghani <gautam@linux.ibm.com>,
Chinmay Rath <rathc@linux.ibm.com>
Subject: [PATCH 7/8] ppc/pnv: Remove Power8E and Power8NVL CPUs
Date: Tue, 23 Jun 2026 19:49:32 +0530 [thread overview]
Message-ID: <20260623141933.577981-8-adityag@linux.ibm.com> (raw)
In-Reply-To: <20260623141933.577981-1-adityag@linux.ibm.com>
Power8E and Power8NVL were deprecated since QEMU 10.1, with
commit 264a604e7163 ("target/ppc: Deprecate Power8E and Power8NVL")
Remove the corresponding 8E and 8NVL CPU cores from spapr/pseries
Also, with no use of 8E and 8NVL, in powernv chips or spapr cores,
remove the CPU definitions for the cores
Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Signed-off-by: Aditya Gupta <adityag@linux.ibm.com>
---
docs/about/deprecated.rst | 9 ---------
docs/about/removed-features.rst | 8 ++++++++
docs/system/ppc/pseries.rst | 2 +-
hw/ppc/spapr_cpu_core.c | 2 --
target/ppc/cpu-models.c | 6 ------
target/ppc/cpu-models.h | 4 ----
target/ppc/cpu_init.c | 6 ------
target/ppc/kvm.c | 4 +---
8 files changed, 10 insertions(+), 31 deletions(-)
diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst
index 97750f5edc91..3930ef08ed4b 100644
--- a/docs/about/deprecated.rst
+++ b/docs/about/deprecated.rst
@@ -215,15 +215,6 @@ embedded 405 for power management (OCC) and other internal tasks, it
is theoretically possible to use QEMU to model them. Let's keep the
CPU implementation for a while before removing all support.
-Power8E and Power8NVL CPUs and corresponding Pnv chips (since 10.1)
-'''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''
-
-The Power8E and Power8NVL variants of Power8 are not really useful anymore
-in qemu, and are old and unmaintained now.
-
-The CPUs as well as corresponding Power8NVL and Power8E PnvChips will also
-be considered deprecated.
-
System emulator machines
------------------------
diff --git a/docs/about/removed-features.rst b/docs/about/removed-features.rst
index d1bea4d75bb4..f7a2aa326dec 100644
--- a/docs/about/removed-features.rst
+++ b/docs/about/removed-features.rst
@@ -1038,6 +1038,14 @@ initial RISC-V QEMU port. Its usage was always been unclear: users don't know
what to expect from a CPU called 'any', and in fact the CPU does not do anything
special that isn't already done by the default CPUs rv32/rv64.
+Power8E and Power8NVL CPUs (removed in 11.1)
+''''''''''''''''''''''''''''''''''''''''''''
+
+The Power8E and Power8NVL variants of Power8 are not really useful anymore
+in qemu, and are old and unmaintained.
+Hence, the CPUs as well as corresponding Power8NVL and Power8E PnvChips have
+been removed
+
System accelerators
-------------------
diff --git a/docs/system/ppc/pseries.rst b/docs/system/ppc/pseries.rst
index bbc51aa7fcdb..1477028bc5ea 100644
--- a/docs/system/ppc/pseries.rst
+++ b/docs/system/ppc/pseries.rst
@@ -16,7 +16,7 @@ Supported devices
* Multi processor support for many Power processors generations:
- POWER7, POWER7+
- - POWER8, POWER8NVL
+ - POWER8
- POWER9
- Power10
- Power11
diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c
index 41e37103c043..9a9351991c95 100644
--- a/hw/ppc/spapr_cpu_core.c
+++ b/hw/ppc/spapr_cpu_core.c
@@ -408,8 +408,6 @@ static const TypeInfo spapr_cpu_core_type_infos[] = {
DEFINE_SPAPR_CPU_CORE_TYPE("power7_v2.3"),
DEFINE_SPAPR_CPU_CORE_TYPE("power7p_v2.1"),
DEFINE_SPAPR_CPU_CORE_TYPE("power8_v2.0"),
- DEFINE_SPAPR_CPU_CORE_TYPE("power8e_v2.1"),
- DEFINE_SPAPR_CPU_CORE_TYPE("power8nvl_v1.0"),
DEFINE_SPAPR_CPU_CORE_TYPE("power9_v2.0"),
DEFINE_SPAPR_CPU_CORE_TYPE("power9_v2.2"),
DEFINE_SPAPR_CPU_CORE_TYPE("power10_v2.0"),
diff --git a/target/ppc/cpu-models.c b/target/ppc/cpu-models.c
index 26b6debcfc96..aa13654e83e8 100644
--- a/target/ppc/cpu-models.c
+++ b/target/ppc/cpu-models.c
@@ -734,12 +734,8 @@
"POWER7 v2.3")
POWERPC_DEF("power7p_v2.1", CPU_POWERPC_POWER7P_v21, POWER7,
"POWER7+ v2.1")
- POWERPC_DEPRECATED_CPU("power8e_v2.1", CPU_POWERPC_POWER8E_v21, POWER8,
- "POWER8E v2.1", "CPU is unmaintained.")
POWERPC_DEF("power8_v2.0", CPU_POWERPC_POWER8_v20, POWER8,
"POWER8 v2.0")
- POWERPC_DEPRECATED_CPU("power8nvl_v1.0", CPU_POWERPC_POWER8NVL_v10, POWER8,
- "POWER8NVL v1.0", "CPU is unmaintained.")
POWERPC_DEF("power9_v2.0", CPU_POWERPC_POWER9_DD20, POWER9,
"POWER9 v2.0")
POWERPC_DEF("power9_v2.2", CPU_POWERPC_POWER9_DD22, POWER9,
@@ -918,9 +914,7 @@ PowerPCCPUAlias ppc_cpu_aliases[] = {
{ "power7", "power7_v2.3" },
{ "power7+", "power7p_v2.1" },
{ "power7+_v2.1", "power7p_v2.1" },
- { "power8e", "power8e_v2.1" },
{ "power8", "power8_v2.0" },
- { "power8nvl", "power8nvl_v1.0" },
{ "power9", "power9_v2.2" },
{ "power10", "power10_v2.0" },
{ "power11", "power11_v2.0" },
diff --git a/target/ppc/cpu-models.h b/target/ppc/cpu-models.h
index a439eb37ee41..ef019cdb1f3c 100644
--- a/target/ppc/cpu-models.h
+++ b/target/ppc/cpu-models.h
@@ -341,12 +341,8 @@ enum {
CPU_POWERPC_POWER7_v23 = 0x003F0203,
CPU_POWERPC_POWER7P_BASE = 0x004A0000,
CPU_POWERPC_POWER7P_v21 = 0x004A0201,
- CPU_POWERPC_POWER8E_BASE = 0x004B0000,
- CPU_POWERPC_POWER8E_v21 = 0x004B0201,
CPU_POWERPC_POWER8_BASE = 0x004D0000,
CPU_POWERPC_POWER8_v20 = 0x004D0200,
- CPU_POWERPC_POWER8NVL_BASE = 0x004C0000,
- CPU_POWERPC_POWER8NVL_v10 = 0x004C0100,
CPU_POWERPC_POWER9_BASE = 0x004E0000,
CPU_POWERPC_POWER9_DD1 = 0x004E1100,
CPU_POWERPC_POWER9_DD20 = 0x004E1200,
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index a02187ce5afb..96daa7e2ab0b 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -6311,12 +6311,6 @@ static bool ppc_pvr_match_power8(PowerPCCPUClass *pcc, uint32_t pvr, bool best)
if (base == CPU_POWERPC_POWER8_BASE) {
return true;
}
- if (base == CPU_POWERPC_POWER8E_BASE) {
- return true;
- }
- if (base == CPU_POWERPC_POWER8NVL_BASE) {
- return true;
- }
}
if (base != pcc_base) {
return false;
diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c
index b94c2997a07f..78a1c4a8393e 100644
--- a/target/ppc/kvm.c
+++ b/target/ppc/kvm.c
@@ -2437,9 +2437,7 @@ static bool kvmppc_power8_host(void)
#ifdef TARGET_PPC64
{
uint32_t base_pvr = CPU_POWERPC_POWER_SERVER_MASK & mfpvr();
- ret = (base_pvr == CPU_POWERPC_POWER8E_BASE) ||
- (base_pvr == CPU_POWERPC_POWER8NVL_BASE) ||
- (base_pvr == CPU_POWERPC_POWER8_BASE);
+ ret = (base_pvr == CPU_POWERPC_POWER8_BASE);
}
#endif /* TARGET_PPC64 */
return ret;
--
2.54.0
next prev parent reply other threads:[~2026-06-23 14:21 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-23 14:19 [PATCH 0/8] Testcase improvements and Power8E/NVL removal Aditya Gupta
2026-06-23 14:19 ` [PATCH 1/8] tests/functional: Add remote interrupts test for PowerNV Aditya Gupta
2026-06-23 15:47 ` Shivang Upadhyay
2026-06-23 14:19 ` [PATCH 2/8] tests/qtest/pnv_spi: Test Power11 PNV_SPI Aditya Gupta
2026-06-23 14:19 ` [PATCH 3/8] tests/qtest: Add Power11 chip & machine to qtests Aditya Gupta
2026-06-23 15:54 ` Shivang Upadhyay
2026-06-23 14:19 ` [PATCH 4/8] tests/functional: Use default powernv machine instead of power10 Aditya Gupta
2026-06-23 14:19 ` [PATCH 5/8] ppc/pnv: Replace Power8E with Power11 for 'none' machine test Aditya Gupta
2026-06-23 14:19 ` [PATCH 6/8] ppc/pnv: Remove Power8E and Power8NVL pnv chips Aditya Gupta
2026-06-23 14:19 ` Aditya Gupta [this message]
2026-06-23 14:19 ` [PATCH 8/8] MAINTAINERS: Add self as maintainer for PowerNV Aditya Gupta
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