From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from pdx-out-005.esa.us-west-2.outbound.mail-perimeter.amazon.com (pdx-out-005.esa.us-west-2.outbound.mail-perimeter.amazon.com [52.13.214.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9CD2F3859EF; Thu, 2 Jul 2026 19:04:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=52.13.214.179 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783019088; cv=none; b=IHg9FfiD/JbfeG0xX4DQxObylaPWJWloDHYomVk1rHZRXoM9LuvusNO3FMS3JwM7NLFDZ/5vpXG/Fg9uNYRMZkw3QtUenOGkKUJ7wseFt58UGjm55Zs3Wd99njPzji/z+KbL+rorfTZbazOUYOPZT1nghdqGIWlB1pphuL+pCQQ= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783019088; c=relaxed/simple; bh=8tuJxCNBOWXuUagNrDc+bjsm5o3QNE9mkekLHhRL+ko=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=naur8rH3e9JKj12R5sKP6DHImzouZtExOj2xOR+cCdKuLclzCHFssGRIBeQz6Age+sgsX1dRT+FIkTrPdhCi0CZzf9KBno5BpMc49Z54now62DAL79lpMe1+qLimxfm/8blYq0bBRo2ZiEDsX91NuyIMKvQqkdM+eVsvGpgPy1E= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amazon.com; spf=pass smtp.mailfrom=amazon.com; dkim=pass (2048-bit key) header.d=amazon.com header.i=@amazon.com header.b=OcojYJ+Z; arc=none smtp.client-ip=52.13.214.179 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amazon.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=amazon.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=amazon.com header.i=@amazon.com header.b="OcojYJ+Z" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amazon.com; i=@amazon.com; q=dns/txt; s=amazoncorp2; t=1783019086; x=1814555086; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=28PbrJsue24gxCxFzMj1TZNmDll7upM8xjPIwGE2HHc=; b=OcojYJ+Zrz3hbG5Igv5SQqgb2YDwHiU7GMjzim+wovUgOrSwk8pdzRwW MMjMQYdPXlG2dmsmj+bTHTRPdpP80yMEJVha/VuJuQShPcBPBtlC7q5dZ cie6wiF3AqxAcgIuVOP07tUK+9x1xne6No6wWxi31hezg9wt7JDyj2POG UMfOaBvwpUF9gN/lZRbzuAigLkKKQTBb9TQ2Z96qRVPTYIGXdG3LWq/x8 3+Qo9Kgj+6n0faYsfPiBg+UefYYtbEkWRS3EM9ZjwGFOPbcUsFHYab0Fy Nf7/CagFUHfWqpKAtZ+pu8AiRozWng2ru/rJ5jOSYbwthLaEzxcWMoDbr g==; X-CSE-ConnectionGUID: Z1BcOmIYQYKK6k3LUBa7pQ== X-CSE-MsgGUID: 3IFZy54RQYaqxgK0r4k1gA== X-IronPort-AV: E=Sophos;i="6.25,144,1779148800"; d="scan'208";a="22933538" Received: from ip-10-5-9-48.us-west-2.compute.internal (HELO smtpout.naws.us-west-2.prod.farcaster.email.amazon.dev) ([10.5.9.48]) by internal-pdx-out-005.esa.us-west-2.outbound.mail-perimeter.amazon.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Jul 2026 19:04:43 +0000 Received: from EX19MTAUWB001.ant.amazon.com [205.251.233.104:32053] by smtpin.naws.us-west-2.prod.farcaster.email.amazon.dev [10.0.43.112:2525] with esmtp (Farcaster) id 8a338137-edab-4456-8313-f0c7488aa835; Thu, 2 Jul 2026 19:04:42 +0000 (UTC) X-Farcaster-Flow-ID: 8a338137-edab-4456-8313-f0c7488aa835 Received: from EX19D001UWA001.ant.amazon.com (10.13.138.214) by EX19MTAUWB001.ant.amazon.com (10.250.64.248) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA) id 15.2.2562.43; Thu, 2 Jul 2026 19:04:42 +0000 Received: from dev-dsk-congkai-2a-df9e8fab.us-west-2.amazon.com (172.23.251.204) by EX19D001UWA001.ant.amazon.com (10.13.138.214) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA) id 15.2.2562.43; Thu, 2 Jul 2026 19:04:42 +0000 From: Congkai Tan To: Oliver Upton , , CC: Congkai Tan , Marc Zyngier , "Joey Gouly" , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , Will Deacon , Paolo Bonzini , "Jonathan Corbet" , Haris Okanovic , Geoff Blake , Stanislav Spassov , , , , Subject: [PATCH v2 3/3] KVM: arm64: Advertise STALL_SLOT* in PMCEID1 under strict PMUv3 UAPI Date: Thu, 2 Jul 2026 19:04:21 +0000 Message-ID: <20260702190421.420992-4-congkai@amazon.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260702190421.420992-1-congkai@amazon.com> References: <20260702190421.420992-1-congkai@amazon.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: EX19D045UWC004.ant.amazon.com (10.13.139.203) To EX19D001UWA001.ant.amazon.com (10.13.138.214) Skip masking STALL_SLOT, STALL_SLOT_FRONTEND and STALL_SLOT_BACKEND out of PMCEID1 when KVM_ARM_VCPU_PMU_V3_STRICT is set, because this is when PMMIR_EL1.SLOTS is exposed to guests, making these events meaningful for collection. Change the parameter of compute_pmceid1() from arm_pmu to kvm_vcpu, to check if KVM_ARM_VCPU_PMU_V3_STRICT is set. Also updated the signature of compute_pmceid0() for consistency. Signed-off-by: Congkai Tan Reviewed-by: Geoff Blake Reviewed-by: Haris Okanovic Reviewed-by: Stanislav Spassov --- arch/arm64/kvm/pmu-emul.c | 25 +++++++++++++------------ 1 file changed, 13 insertions(+), 12 deletions(-) diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c index 9595bce6519f..89eec5a1a499 100644 --- a/arch/arm64/kvm/pmu-emul.c +++ b/arch/arm64/kvm/pmu-emul.c @@ -851,9 +851,9 @@ static u64 __compute_pmceid(struct arm_pmu *pmu, bool pmceid1) return ((u64)hi[pmceid1] << 32) | lo[pmceid1]; } -static u64 compute_pmceid0(struct arm_pmu *pmu) +static u64 compute_pmceid0(struct kvm_vcpu *vcpu) { - u64 val = __compute_pmceid(pmu, 0); + u64 val = __compute_pmceid(vcpu->kvm->arch.arm_pmu, 0); /* always support SW_INCR */ val |= BIT(ARMV8_PMUV3_PERFCTR_SW_INCR); @@ -862,32 +862,33 @@ static u64 compute_pmceid0(struct arm_pmu *pmu) return val; } -static u64 compute_pmceid1(struct arm_pmu *pmu) +static u64 compute_pmceid1(struct kvm_vcpu *vcpu) { - u64 val = __compute_pmceid(pmu, 1); + u64 val = __compute_pmceid(vcpu->kvm->arch.arm_pmu, 1); /* - * Don't advertise STALL_SLOT*, as PMMIR_EL0 is handled - * as RAZ + * If KVM_ARM_VCPU_PMU_V3_STRICT is not set, PMMIR_EL1 is + * unconditionally RAZ, so don't advertise STALL_SLOT* events. */ - val &= ~(BIT_ULL(ARMV8_PMUV3_PERFCTR_STALL_SLOT - 32) | - BIT_ULL(ARMV8_PMUV3_PERFCTR_STALL_SLOT_FRONTEND - 32) | - BIT_ULL(ARMV8_PMUV3_PERFCTR_STALL_SLOT_BACKEND - 32)); + if (!kvm_vcpu_has_pmuv3_strict(vcpu)) + val &= ~(BIT_ULL(ARMV8_PMUV3_PERFCTR_STALL_SLOT - 32) | + BIT_ULL(ARMV8_PMUV3_PERFCTR_STALL_SLOT_FRONTEND - 32) | + BIT_ULL(ARMV8_PMUV3_PERFCTR_STALL_SLOT_BACKEND - 32)); + return val; } u64 kvm_pmu_get_pmceid(struct kvm_vcpu *vcpu, bool pmceid1) { - struct arm_pmu *cpu_pmu = vcpu->kvm->arch.arm_pmu; unsigned long *bmap = vcpu->kvm->arch.pmu_filter; u64 val, mask = 0; int base, i, nr_events; if (!pmceid1) { - val = compute_pmceid0(cpu_pmu); + val = compute_pmceid0(vcpu); base = 0; } else { - val = compute_pmceid1(cpu_pmu); + val = compute_pmceid1(vcpu); base = 32; } -- 2.50.1