From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6DBB0442139; Tue, 7 Jul 2026 18:44:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.11 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783449855; cv=none; b=iQs1PhgpfiTV+7MWVtON8VxJ7qDSpimgefiCXDcDFMarl2O7aiqT2FMXSCNelhZBAKaD+wzI2wP/+g6qWMCT7xN9P/NUCZ06FhSKCHI8bWadeURVvcBSC/D4+sIbAcw62Ip2CjixXBlRtM2x1G+woL3SreQ65yShUlQkUrGPRDo= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783449855; c=relaxed/simple; bh=APnv8+QwFLXmQdxywqFdU7jqpMSYH+RFILsagEHXliA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=CSKH5pvNuxYD4AD3IrkHw/pnzyjsCS0uEPStbXqTc2gNZ7B+xOt7K09EsFuSLtrlt70yWWv0sHp0pKDZ+CuM64rbwfHEdWJp6hae7/Om76lJ3DcvoqdDfVlyoavxV0pFqa+bNrG913C5W1vi9OKkkJ500yMAT3xpG2WGkZjgiVc= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=E7ELYtKp; arc=none smtp.client-ip=192.198.163.11 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="E7ELYtKp" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1783449847; x=1814985847; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=APnv8+QwFLXmQdxywqFdU7jqpMSYH+RFILsagEHXliA=; b=E7ELYtKp2DW7XO0x/jZ9N6+nxSJSIBGUCjhHL0TFbbudgWkF6ZxdLc9W oLfX2t+xLQSQNokoq5m6VfWaa5ioq4HWv6H+DZtNVdcZIwNwKeAQp9pxx ApxG7vdJhizfYmaC8+CZbFPEh6JAtFyh/jCY5N2If6TgaPOA9VIlaIBN2 ENgqhSYWN2vgLNSQ9bHJGb1OcE844qCzj40elViiQAye4ENDO0dj0/8CB /aBLwu7GugeAwePKB3mylEI0RzI0fEDd4bHUp3kkjz3pShrnKFAzxIBAy kUy7RC0EVFAyTv9RfAMHaXhlLuKVkut8V+HkJVTO44kgMOSEJH/iF2n98 A==; X-CSE-ConnectionGUID: k7Qf3VcsTjeizTG2j9ljSQ== X-CSE-MsgGUID: IFFRVDjrQweC6AQv8yd1zw== X-IronPort-AV: E=McAfee;i="6800,10657,11840"; a="94713897" X-IronPort-AV: E=Sophos;i="6.25,153,1779174000"; d="scan'208";a="94713897" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by fmvoesa105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2026 11:43:59 -0700 X-CSE-ConnectionGUID: ZhfXiDSsQI+U4Hkfq7EY/Q== X-CSE-MsgGUID: 3ab+m/DBQt+Cmkx87SmUOg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.25,153,1779174000"; d="scan'208";a="277279328" Received: from 9cc2c43eec6b.jf.intel.com ([10.54.77.29]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2026 11:43:59 -0700 From: Zide Chen To: Sean Christopherson , Paolo Bonzini , Peter Zijlstra Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Jim Mattson , Mingwei Zhang , Zide Chen , Das Sandipan , Shukla Manali , Dapeng Mi , Falcon Thomas , Xudong Hao Subject: [PATCH 11/15] KVM: x86/pmu: Emulate streamlined Freeze-LBR-on-PMI Date: Tue, 7 Jul 2026 11:34:01 -0700 Message-ID: <20260707183405.15571-12-zide.chen@intel.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260707183405.15571-1-zide.chen@intel.com> References: <20260707183405.15571-1-zide.chen@intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit PerfMon v4 streamlined the Freeze-LBR-on-PMI mechanism. When DEBUGCTLMSR_FREEZE_LBRS_ON_PMI is set and a PMI fires, hardware sets IA32_PERF_GLOBAL_STATUS.LBR_Frz instead of clearing DEBUGCTLMSR_LBR. Guest PerfMon v4+ is supported under mediated vPMU only. When KVM relays a guest-induced PMI, the mediated vPMU framework already propagates IA32_PERF_GLOBAL_STATUS.LBR_Frz, and no additional handling is required. For PMIs generated by KVM-emulated PMU events, however, KVM must emulate IA32_PERF_GLOBAL_STATUS.LBR_Frz so that guest LBR recording is frozen as required by the architectural behavior. Signed-off-by: Zide Chen --- arch/x86/kvm/vmx/pmu_intel.c | 47 ++++++++++++++++++++++-------------- 1 file changed, 29 insertions(+), 18 deletions(-) diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c index cb6f9c272e03..556c119d5e91 100644 --- a/arch/x86/kvm/vmx/pmu_intel.c +++ b/arch/x86/kvm/vmx/pmu_intel.c @@ -660,6 +660,8 @@ static void intel_pmu_refresh(struct kvm_vcpu *vcpu) pmu->global_status_rsvd = pmu->global_ctrl_rsvd & ~(GLOBAL_STATUS_BUFFER_OVF | GLOBAL_STATUS_COND_CHG); + if (pmu->version > 3) + pmu->global_status_rsvd &= ~GLOBAL_STATUS_LBRS_FROZEN; if (vmx_pt_mode_is_host_guest()) pmu->global_status_rsvd &= ~GLOBAL_STATUS_TRACE_TOPAPMI; @@ -718,32 +720,41 @@ static void intel_pmu_reset(struct kvm_vcpu *vcpu) } /* - * Emulate LBR_On_PMI behavior for 1 < pmu.version < 4. - * - * If Freeze_LBR_On_PMI = 1, the LBR is frozen on PMI and - * the KVM emulates to clear the LBR bit (bit 0) in IA32_DEBUGCTL. - * - * Guest needs to re-enable LBR to resume branches recording. + * Emulate legacy and streamlined Freeze_LBR_On_PMI behavior. + * In either case, guest needs to re-enable LBR to resume branches recording. */ -static void intel_pmu_legacy_freezing_lbrs_on_pmi(struct kvm_vcpu *vcpu) +static void intel_pmu_freeze_lbr_on_pmi(struct kvm_vcpu *vcpu) { - u64 data = vmx_guest_debugctl_read(); + u8 version; + u64 data; - if (data & DEBUGCTLMSR_FREEZE_LBRS_ON_PMI) { - data &= ~DEBUGCTLMSR_LBR; - vmx_guest_debugctl_write(vcpu, data); + if (!intel_pmu_lbr_is_enabled(vcpu)) + return; + + data = vmx_guest_debugctl_read(); + version = vcpu_to_pmu(vcpu)->version; + + if (!(data & DEBUGCTLMSR_FREEZE_LBRS_ON_PMI)) + return; + + if (version > 1 && version < 4) { + if (data & DEBUGCTLMSR_LBR) { + data &= ~DEBUGCTLMSR_LBR; + vmx_guest_debugctl_write(vcpu, data); + } + } else if (vcpu_to_lbr_desc(vcpu)->msr_passthrough && + kvm_vcpu_has_mediated_pmu(vcpu)) { + /* + * This will be restored to guest before VM-Entry, setting + * LBR_Frz to freeze LBR recording until the guest clears it. + */ + vcpu_to_pmu(vcpu)->global_status |= GLOBAL_STATUS_LBRS_FROZEN; } } static void intel_pmu_deliver_pmi(struct kvm_vcpu *vcpu) { - u8 version = vcpu_to_pmu(vcpu)->version; - - if (!intel_pmu_lbr_is_enabled(vcpu)) - return; - - if (version > 1 && version < 4) - intel_pmu_legacy_freezing_lbrs_on_pmi(vcpu); + intel_pmu_freeze_lbr_on_pmi(vcpu); } static void vmx_update_intercept_for_lbr_msrs(struct kvm_vcpu *vcpu, bool set) -- 2.54.0