Kernel KVM virtualization development
 help / color / mirror / Atom feed
From: sashiko-bot@kernel.org
To: "Charlie Jenkins" <thecharlesjenkins@gmail.com>
Cc: kvm@vger.kernel.org
Subject: Re: [PATCH v3 11/17] KVM: riscv: selftests: Add mmio test
Date: Wed, 08 Jul 2026 03:59:09 +0000	[thread overview]
Message-ID: <20260708035910.0664E1F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260707-riscv_insn_table-v3-11-3f8e5f75ba97@gmail.com>

Thank you for your contribution! Sashiko AI review found 4 potential issue(s) to consider:

New issues:
- [Medium] The selftest unconditionally creates a KVM_DEV_TYPE_TEST device without checking for host support, causing hard failures on standard kernels.
- [Medium] Missing "memory" clobber in inline assembly allows compiler to reorder or eliminate MMIO stores and local variable initializations.
- [Low] Overly broad inline assembly constraints for RISC-V compressed instructions will cause intermittent assembler errors.

Pre-existing issues:
- [High] The KVM MMIO test device fails to unregister its MMIO bus device on teardown, leading to a Use-After-Free when the memory is subsequently freed.
--

--- Patch [11]: [PATCH v3 11/17] KVM: riscv: selftests: Add mmio test ---
commit 39a55e4a273642e2ad8e96502e3f7d6eb84c69ad
Author: Charlie Jenkins <thecharlesjenkins@gmail.com>

KVM: riscv: selftests: Add mmio test

This commit adds a test to validate that KVM properly emulates reads
and writes to a KVM test device. It checks all load and store
instructions emulated by KVM for RISC-V.

> diff --git a/tools/testing/selftests/kvm/riscv/mmio_test.c b/tools/testing/selftests/kvm/riscv/mmio_test.c
> new file mode 100644
> index 0000000000000..ea3837771a333
> --- /dev/null
> +++ b/tools/testing/selftests/kvm/riscv/mmio_test.c
> @@ -0,0 +1,189 @@
> +// SPDX-License-Identifier: GPL-2.0-only
[ ... ]
> +#define test_standard_read(len, instruction, name, options)					\
> +static void test_##name(void)									\
> +{												\
> +	unsigned long mmio_result, reference_result;						\
> +	/* Configure the MMIO to return 0xff for each byte to check sign extension */		\
> +	unsigned long reference = ((unsigned long)-1 >> ((sizeof(long) - len) * 8));		\
> +	*((unsigned long *)MMIO_TEST_REGION) = reference;					\
> +	/* Check that reads through MMIO are equivalent to standard reads. */			\
> +	asm volatile (										\
> +		".option push\n"								\
> +		options										\
> +		#instruction "	%[mmio_res], 0(%[region])\n"					\
> +		#instruction "	%[ref_res], 0(%[ref])\n"					\
> +		".option pop\n"									\
> +		: [mmio_res] "=&cr" (mmio_result), [ref_res] "=&cr" (reference_result)		\
> +		: [region] "cr" (MMIO_TEST_REGION), [ref] "cr" (&reference)			\
> +	);											\

[Severity: Medium]
Since the pointer to MMIO_TEST_REGION lacks a volatile qualifier and the
asm volatile block lacks a "memory" clobber, can the compiler optimize away
or reorder the store to MMIO_TEST_REGION?

GCC's dead store elimination might eliminate the initialization store since
it does not see any memory inputs to the assembly block, which could cause
the guest to execute with uninitialized memory and fail intermittently.

[Severity: Low]
Will using the "cr" constraint cause intermittent assembler errors for
compressed instructions?

For instructions like c.lw and c.sw, the assembler strictly requires
registers in the x8-x15 range. If GCC allocates a general register outside
this range, will the GNU Assembler fail with illegal operands?

> +	GUEST_ASSERT_EQ(mmio_result, reference_result);						\
> +	GUEST_DONE();										\
> +}
> +
> +#define test_sp_read(len, instruction, name)							\
> +static void test_##name(void)									\
> +{												\
> +	unsigned long mmio_result, reference_result;						\
> +	unsigned long tmp;									\
> +	/* Configure the MMIO to return 0xff for each byte to check sign extension */		\
> +	unsigned long reference = ((unsigned long)-1 >> ((sizeof(long) - len) * 8));		\
> +	*(((unsigned long *)MMIO_TEST_REGION)) = reference;					\

[Severity: Medium]
Similarly to test_standard_read(), could the missing "memory" clobber or
volatile qualifier here allow the compiler to eliminate the reference store?

[ ... ]
> +#define test_standard_write(len, write, read, name, options)					\
> +static void test_##name(void)									\
> +{												\
> +	unsigned long result;									\
> +	unsigned long reference = (0x5555555555555555ULL >> ((sizeof(long) - len) * 8));	\
> +	/* Check that we can write and then read the same value. */				\
> +	asm volatile (										\
> +		".option push\n"								\
> +		options										\
> +		#write "	%[ref], 0(%[region])\n"						\
> +		#read "		%[res], 0(%[region])\n"						\
> +		".option pop\n"									\
> +		: [res] "=&cr" (result)								\
> +		: [region] "cr" (MMIO_TEST_REGION), [ref] "cr" (reference)			\
> +	);											\

[Severity: Low]
Could the "cr" constraint also cause assembler errors here when the macro
is expanded for compressed instructions like c.sw and c.lw?

[ ... ]
> +static void run(void *guest_code, char *instruction)
> +{
> +	int fd;
> +	struct ucall uc;
> +	struct kvm_vm *vm;
> +	struct kvm_vcpu *vcpu;
> +
> +	vm = vm_create_with_one_vcpu(&vcpu, guest_code);
> +	fd = kvm_create_device(vm, KVM_DEV_TYPE_TEST);

[Severity: Medium]
If the host kernel does not have CONFIG_KVM_MMIO_TEST enabled, will
kvm_create_device() fail with -ENODEV and cause the test to abort?

Would it be better to dynamically check for capabilities and skip
gracefully (for example, by using TEST_REQUIRE() or similar test helpers)
instead of failing?


[Severity: High]
This is a pre-existing issue, but there appears to be a use-after-free
during teardown in virt/kvm/mmio_test.c.

In mmio_test_destroy():

virt/kvm/mmio_test.c:mmio_test_destroy() {
        ...
        struct mmio_test *mmio_test = kvm_to_mmio_test_dev(dev);
        ...
        kvm_io_bus_unregister_dev(dev->kvm, KVM_MMIO_BUS, &mmio_test->dev);
        kfree(dev->private);
}

Does kvm_to_mmio_test_dev() expect a struct kvm_io_device pointer rather
than a struct kvm_device pointer?

If so, container_of() might compute an invalid pointer, causing
kvm_io_bus_unregister_dev() to fail to unregister the actual mmio_test->dev.
When the structure is later freed, will this leave a dangling pointer in
the KVM MMIO bus that triggers a use-after-free on subsequent MMIO
accesses?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260707-riscv_insn_table-v3-0-3f8e5f75ba97@gmail.com?part=11

  reply	other threads:[~2026-07-08  3:59 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-07-08  3:34 [PATCH v3 00/17] riscv: Generate riscv instruction functions Charlie Jenkins
2026-07-08  3:34 ` [PATCH v3 01/17] riscv: Introduce instruction table generation Charlie Jenkins
2026-07-08  3:50   ` sashiko-bot
2026-07-09  6:23     ` Charlie Jenkins
2026-07-08  3:34 ` [PATCH v3 02/17] riscv: alternatives: Use generated instruction headers for patching code Charlie Jenkins
2026-07-08  3:45   ` sashiko-bot
2026-07-08  3:34 ` [PATCH v3 03/17] riscv: kgdb: Use generated instruction headers Charlie Jenkins
2026-07-08  3:34 ` [PATCH v3 04/17] riscv: Add kprobes instruction simulation KUnit Charlie Jenkins
2026-07-08  3:51   ` sashiko-bot
2026-07-08  3:34 ` [PATCH v3 05/17] riscv: kprobes: Use generated instruction headers Charlie Jenkins
2026-07-08  3:52   ` sashiko-bot
2026-07-08  3:34 ` [PATCH v3 06/17] riscv: cfi: " Charlie Jenkins
2026-07-08  3:34 ` [PATCH v3 07/17] riscv: Maintain epc on misaligned emulation error Charlie Jenkins
2026-07-08  3:55   ` sashiko-bot
2026-07-08  3:34 ` [PATCH v3 08/17] riscv: Use generated instruction headers for misaligned loads/stores Charlie Jenkins
2026-07-08  3:49   ` sashiko-bot
2026-07-08  3:34 ` [PATCH v3 09/17] riscv: kvm: Use generated instruction headers for csr code Charlie Jenkins
2026-07-08  3:48   ` sashiko-bot
2026-07-08  3:34 ` [PATCH v3 10/17] KVM: device: Add test device Charlie Jenkins
2026-07-08  3:48   ` sashiko-bot
2026-07-08  3:34 ` [PATCH v3 11/17] KVM: riscv: selftests: Add mmio test Charlie Jenkins
2026-07-08  3:59   ` sashiko-bot [this message]
2026-07-08  3:34 ` [PATCH v3 12/17] riscv: kvm: Use generated instruction headers for mmio emulation Charlie Jenkins
2026-07-08  4:01   ` sashiko-bot
2026-07-08  3:34 ` [PATCH v3 13/17] riscv: kvm: Add emulated test csr Charlie Jenkins
2026-07-08  4:00   ` sashiko-bot
2026-07-08  3:34 ` [PATCH v3 14/17] KVM: riscv: selftests: Add csr emulation test Charlie Jenkins
2026-07-08  3:58   ` sashiko-bot
2026-07-08  3:34 ` [PATCH v3 15/17] riscv: kvm: Use generated instruction headers for csr emulation Charlie Jenkins
2026-07-08  4:04   ` sashiko-bot
2026-07-08  3:34 ` [PATCH v3 16/17] riscv: kexec: Use generated instruction headers for kexec relocations Charlie Jenkins
2026-07-08  4:01   ` sashiko-bot
2026-07-08  3:34 ` [PATCH v3 17/17] riscv: Remove unused instruction headers Charlie Jenkins
2026-07-08  4:09   ` sashiko-bot
2026-07-09  6:26 ` [syzbot ci] Re: riscv: Generate riscv instruction functions syzbot ci

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20260708035910.0664E1F000E9@smtp.kernel.org \
    --to=sashiko-bot@kernel.org \
    --cc=kvm@vger.kernel.org \
    --cc=sashiko-reviews@lists.linux.dev \
    --cc=thecharlesjenkins@gmail.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox