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Fri, 10 Jul 2026 18:23:31 -0400 (EDT) Date: Fri, 10 Jul 2026 16:23:22 -0600 From: Alex Williamson To: Cc: , , , , , , , , , , , , , , , , , , , , alex@shazbot.org Subject: Re: [PATCH v3 05/11] vfio: UAPI for CXL Type-2 device passthrough Message-ID: <20260710162322.012be635@shazbot.org> In-Reply-To: <20260625165407.1769572-6-mhonap@nvidia.com> References: <20260625165407.1769572-1-mhonap@nvidia.com> <20260625165407.1769572-6-mhonap@nvidia.com> X-Mailer: Claws Mail 4.4.0 (GTK 3.24.52; x86_64-pc-linux-gnu) Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit On Thu, 25 Jun 2026 22:24:01 +0530 wrote: > diff --git a/include/uapi/linux/vfio.h b/include/uapi/linux/vfio.h > index 5de618a3a5ee..3707d53c4de5 100644 > --- a/include/uapi/linux/vfio.h > +++ b/include/uapi/linux/vfio.h > @@ -215,6 +215,7 @@ struct vfio_device_info { > #define VFIO_DEVICE_FLAGS_FSL_MC (1 << 6) /* vfio-fsl-mc device */ > #define VFIO_DEVICE_FLAGS_CAPS (1 << 7) /* Info supports caps */ > #define VFIO_DEVICE_FLAGS_CDX (1 << 8) /* vfio-cdx device */ > +#define VFIO_DEVICE_FLAGS_CXL (1 << 9) /* vfio-cxl Type-2 device */ Would we define a different flag for type-1/3 if we ever found a need to expose them through vfio? > __u32 num_regions; /* Max region index + 1 */ > __u32 num_irqs; /* Max IRQ index + 1 */ > __u32 cap_offset; /* Offset within info struct of first cap */ > @@ -257,6 +258,36 @@ struct vfio_device_info_cap_pci_atomic_comp { > __u32 reserved; > }; > > +/* > + * VFIO_DEVICE_INFO capability for CXL Type-2 passthrough devices. > + * Present when VFIO_DEVICE_FLAGS_CXL is set on vfio_device_info::flags. > + * > + * @flags: VFIO_CXL_CAP_HOST_FIRMWARE_COMMITTED indicates the host CXL > + * subsystem committed the endpoint HDM decoder. > + * @hdm_region_idx: VFIO region index for the HDM memory region > + * (subtype VFIO_REGION_SUBTYPE_CXL). > + * @comp_reg_region_idx: VFIO region index for the CXL Component > + * Register shadow (subtype VFIO_REGION_SUBTYPE_CXL_COMP_REGS). These regions are self describing via the noted CXL subtypes, what's the purpose of double reporting them here? > + * @comp_reg_bar: PCI BAR index that contains the CXL component > + * register block. Get-region-info on this BAR returns a > + * VFIO_REGION_INFO_CAP_SPARSE_MMAP that excludes the CXL block. > + * @comp_reg_offset: byte offset of the CXL component register block > + * within @comp_reg_bar. > + * @comp_reg_size: byte size of the CXL component register block. Why don't we describe all of these via a capability on the relevant region info? Does that leave this device level capability describing the device as type-2 (by existence), with only a flags field to declare HDM as firmware committed, for future compatibility should we support non-fw committed? Thanks, Alex