Re: [PATCH v5 5/5] LoongArch: KVM: Use internal API to deliver interrupt in kernel mode

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:

New issues:
- [Medium] The commit silently includes a critical fix for a guest-triggerable out-of-bounds array access in the EIOINTC emulation.

Pre-existing issues:
- [Critical] Unvalidated 'msi.data' from userspace causes severe out-of-bounds memory accesses in 'eiointc_set_irq' and 'eiointc_update_irq'.
--

--- Patch [5]: [PATCH v5 5/5] LoongArch: KVM: Use internal API to deliver interrupt in kernel mode ---
commit f180398d8de8f24b25d2d879c17f336978ed95e1
Author: Bibo Mao <maobibo@loongson.cn>

LoongArch: KVM: Use internal API to deliver interrupt in kernel mode
    
API kvm_vcpu_ioctl_interrupt() is mainly to used to deliver interrupt
from user mode, and internal APIs kvm_queue_irq() and kvm_dequeue_irq()
are used in kernel mode.

Also move IPI inject and ack within lock protection to avoid contention
in ipi_set() and ipi_clear().

> diff --git a/arch/loongarch/kvm/intc/eiointc.c b/arch/loongarch/kvm/intc/eiointc.c
> index fd089d54da103..e04aadbd68db9 100644
> --- a/arch/loongarch/kvm/intc/eiointc.c
> +++ b/arch/loongarch/kvm/intc/eiointc.c
> @@ -17,7 +17,8 @@ static void eiointc_set_sw_coreisr(struct loongarch_eiointc *s)
>  		if (!(s->status & BIT(EIOINTC_ENABLE_INT_ENCODE))) {
>  			ipnum = count_trailing_zeros(ipnum);
>  			ipnum = ipnum < 4 ? ipnum : 0;
> -		}
> +		} else if (ipnum >= LOONGSON_IP_NUM)
> +			ipnum = 0;

[Severity: Medium]
This looks like a fix for an out-of-bounds array access, as ipnum is used to
index into s->sw_coreisr[][] shortly after this.

Should this fix be documented in the commit message or split into a separate
patch so it can be properly tracked and backported?

[ ... ]

> @@ -36,13 +37,13 @@ static void eiointc_update_irq(struct loongarch_eiointc *s, int irq, int level)
>  {
>  	int ipnum, cpu, found;
>  	struct kvm_vcpu *vcpu;
>  
>  	ipnum = (s->ipmap >> (irq / 32 * 8)) & 0xff;
>  	if (!(s->status & BIT(EIOINTC_ENABLE_INT_ENCODE))) {
>  		ipnum = count_trailing_zeros(ipnum);
>  		ipnum = ipnum < 4 ? ipnum : 0;
> -	}
> +	} else if (ipnum >= LOONGSON_IP_NUM)
> +		ipnum = 0;
>  
>  	cpu = s->sw_coremap[irq];

[Severity: Critical]
This is a pre-existing issue, but does this code perform an out-of-bounds read
or write if irq is greater than or equal to EIOINTC_IRQS (256)?

In pch_msi_set_irq(), the untrusted 32-bit e->msi.data is passed directly as
the irq index:

arch/loongarch/kvm/intc/pch_pic.c:pch_msi_set_irq() {
    ...
    eiointc_set_irq(kvm->arch.eiointc, e->msi.data, level);
    ...
}

eiointc_set_irq() then performs a bitwise operation on the 256-bit isr array
without bounds checking:

arch/loongarch/kvm/intc/eiointc.c:eiointc_set_irq() {
    ...
    level ? __set_bit(irq, isr) : __clear_bit(irq, isr);
    eiointc_update_irq(s, irq, level);
    ...
}

And here in eiointc_update_irq(), it accesses s->sw_coremap[irq].

If e->msi.data from userspace or guest is >= 256, could this cause host kernel
memory corruption?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260714072520.2745942-1-maobibo@loongson.cn?part=5