From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9901E472F90; Wed, 22 Jul 2026 07:43:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784706183; cv=none; b=rHr8FIL+1o9KVspOTH57jaYufEeusWsrUaZHkpmbRbj4BrGx/xnYjrZPxRRFN894Z44tK+8eW3XlFfzFGvtN8Fo8gQaKotDFitL+ZjaSA7CnmWThz3FYTPr63ioDFF8HFfCiVTzpv8idB6IxCJSFIf+dUrwUY9Q8XeATISCrhjg= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784706183; c=relaxed/simple; bh=vM5rIUUKoUwYtebnDOmRSnQ7qOWjuDekPplXzX53rxA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Lc5FY3r9SY0gZQFQv6CYl8oZbdLKEUhfin7oAON4pf/5gkEzaI+xnvuuyYxmfhj/jXMMcOgU+8DQLufFWu76rcQnDvy+S5/ZGXZb/YZCDWaWuFTjqJM0nMAmX7t/UPTT6Za42JiiepZ9/F32PBgHx3MPD1da9AJrqUeFM1E86sY= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=OdyhEVxX; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="OdyhEVxX" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 772461F01561; Wed, 22 Jul 2026 07:43:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1784706180; bh=F1AT8pfTT5H3v1VSsbczUJFUDFVFL+qUil+wR6QR9Z4=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=OdyhEVxXoqKa25VJptJXxiw45sOAbru7dSEqqmxiVwfQOeFYC2hGRNRRNlyZpFDPl x1DHZf+CX8CYtUz2e3jlH0pOe1BZb39KbXVP9CfckCRbIV2QbqG0sWqJmymBEZzQIw rAdrnRZFKz08hKxBBxVLxqXJspNSfBti8FdvyjVIyJA7roufWa2FJBwmlKNduaFjtB V/ERBoX5H8XhwCTwrBRyRPhk193vonYQxL/uUmfqLkd1svloJ9Lw9SOlHOyN2EAJC+ STny7t1BlhB8/EjXcvHhIWzeCX/MTvTe+VAe6RcsQJe0B5Dx5ZCCXZ77XKc7TiutDS 4+olmh+3GHQqA== Received: from sofa.misterjones.org ([185.219.108.64] helo=valley-girl.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1wmRbW-00000007VfN-32sq; Wed, 22 Jul 2026 07:42:58 +0000 From: Marc Zyngier To: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org Cc: Steffen Eiden , Joey Gouly , Suzuki K Poulose , Oliver Upton , Zenghui Yu , Yao Yuan , Wei-Lin Chang Subject: [PATCH v3 20/28] KVM: arm64: Add sanitisation for NVHCR_EL2 Date: Wed, 22 Jul 2026 08:42:26 +0100 Message-ID: <20260722074234.3330999-21-maz@kernel.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260722074234.3330999-1-maz@kernel.org> References: <20260722074234.3330999-1-maz@kernel.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, seiden@linux.ibm.com, joey.gouly@arm.com, suzuki.poulose@arm.com, oupton@kernel.org, yuzenghui@huawei.com, yaoyuan@linux.alibaba.com, weilin.chang@arm.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Just like any other VNCR-based register, NVHCR_EL2 requires some level of sanitisation. Being specified as a live copy of HCR_EL2, it adopts the exact same format, but depends on FEAT_NV3 instead. A subtle aspect is that we only want to apply the sanitisation if FEAT_NV3 is actually present, as the VNCR location is otherwise used to back accesses to HCR_EL2. Signed-off-by: Marc Zyngier --- arch/arm64/kvm/config.c | 15 +++++++++++++++ arch/arm64/kvm/nested.c | 4 ++++ 2 files changed, 19 insertions(+) diff --git a/arch/arm64/kvm/config.c b/arch/arm64/kvm/config.c index 467f57eb8e6bb..1053676551aff 100644 --- a/arch/arm64/kvm/config.c +++ b/arch/arm64/kvm/config.c @@ -1019,6 +1019,9 @@ static const struct reg_bits_to_feat_map hcr_feat_map[] = { static const DECLARE_FEAT_MAP(hcr_desc, HCR_EL2, hcr_feat_map, FEAT_AA64EL2); +static const DECLARE_FEAT_MAP(nvhcr_desc, NVHCR_EL2, + hcr_feat_map, FEAT_NV3); + static const struct reg_bits_to_feat_map sctlr2_feat_map[] = { NEEDS_FEAT(SCTLR2_EL1_NMEA | SCTLR2_EL1_EASE, @@ -1393,6 +1396,7 @@ void __init check_feature_map(void) check_reg_desc(&hdfgwtr2_desc); check_reg_desc(&hcrx_desc); check_reg_desc(&hcr_desc); + check_reg_desc(&nvhcr_desc); check_reg_desc(&sctlr2_desc); check_reg_desc(&tcr2_el2_desc); check_reg_desc(&sctlr_el1_desc); @@ -1592,6 +1596,17 @@ struct resx get_reg_fixed_bits(struct kvm *kvm, enum vcpu_sysreg reg) case HCR_EL2: resx = compute_reg_resx_bits(kvm, &hcr_desc, 0, 0); break; + case NVHCR_EL2: + /* + * Only apply sanitisation if we do have FEAT_NV3. + * Otherwise, the register aliases with HCR_EL2 in VNCR, + * and we're better off relying on data transfers between + * NVHCR_EL2 and HCR_EL2 to sanitise things. + */ + resx = (kvm_has_nv3(kvm) ? + compute_reg_resx_bits(kvm, &nvhcr_desc, 0, 0) : + (typeof(resx)){}); + break; case SCTLR2_EL1: case SCTLR2_EL2: resx = compute_reg_resx_bits(kvm, &sctlr2_desc, 0, 0); diff --git a/arch/arm64/kvm/nested.c b/arch/arm64/kvm/nested.c index 35a1c42ad3f84..f646894fec9a9 100644 --- a/arch/arm64/kvm/nested.c +++ b/arch/arm64/kvm/nested.c @@ -1830,6 +1830,10 @@ int kvm_init_nv_sysregs(struct kvm_vcpu *vcpu) resx = get_reg_fixed_bits(kvm, HCR_EL2); set_sysreg_masks(kvm, HCR_EL2, resx); + /* NVHCR_EL2 */ + resx = get_reg_fixed_bits(kvm, NVHCR_EL2); + set_sysreg_masks(kvm, NVHCR_EL2, resx); + /* HCRX_EL2 */ resx = get_reg_fixed_bits(kvm, HCRX_EL2); set_sysreg_masks(kvm, HCRX_EL2, resx); -- 2.47.3