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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: WmYbyPBGP/MYkhpgMgl27M75de1he5U89qLa9WIsIgpL7qE3RehDR3W68GlL0JLqX8qnN1Bjf4LblIu5ArF3AnFKffKh17AauetCZfZWqFmTCnfzW3bx9QDndzFlSpO6HOikDuREXYvJIeQpzt97OEx8kA3tA7yi0HOeFyir0d5/JyQqH3bVU7VaKzQrGU1g1MxLMwK+8YAMDCa52iLrVgIVkg2P3ylh4Lhh1PO+XB3jT1hM7LSA8oYnqJ89izDZswP8rBQ2kLGjf0UqtxUDB+slmP36fe7LsWsRyJ1jBF47T/Yhjn91kJm0OtmxalhHMnTL8QzzRs5Bf4n6gNO8z6QDpvjDhDVXVCoKjZIfxD6MFhkUVAblnBsslGYbzrLBRcZFrRs732LQhucL/3/kDOCS/wUEJw81rLsfAE2A82YHf0JFMHyUtxa4YYV63f9E X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Aug 2026 11:13:11.3522 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0820b46c-2e36-4051-950c-08def474de35 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[4.158.2.129];Helo=[outbound-uk1.az.dlp.m.darktrace.com] X-MS-Exchange-CrossTenant-AuthSource: DB1PEPF00039231.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: GV2PR08MB9302 Hi all, This series builds on the initial vGICv5 support [1] and adds support for the GICv5 IRS, as described by the GICv5 (EAC0) specification [2]. With this, a GICv5 guest is no longer restricted to PPIs, and can make use of SPIs and LPIs as well. With SPIs and LPIs available, this series makes it possible to boot a full Linux guest on the Arm FVP model [3], using the setup described in Lorenzo's GICv5 Linux software enablement guide [4]. In addition, GICv5 IPIs are typically implemented as LPIs, so LPI support is what makes guests with more than one vCPU possible. The corresponding kvmtool changes are available separately [5]. With these changes, `--irqchip=3Dgicv5` works now. The `--irqchip=3Dgicv5-its` configuration does not work with this series, as ITS/MSI support is not included here. The IRS is created as part of the vgic-v5 device, and is not a separate KVM device. This is because implementing the CPU interface alone would limit a guest to a single vCPU and PPIs only. Hence, the IRS is bundled into the VGIC, much like the distributor for GICv3. The series adds the host-side plumbing needed for KVM to interact with the physical IRS, including VM and VPE table management, VPE residency, and VPE doorbells. It also adds an emulated IRS MMIO interface for the guest, together with the UAPI needed for userspace to configure the IRS address and to save/restore the IRS and IST state. The main pieces are: * Host IRS capability discovery and configuration frame plumbing. * Allocation and management of the GICv5 VM table, VPE table, VMTEs, VPEs, and host-backed guest IST storage. * VPE residency and doorbell handling, allowing the IRS to select SPIs and LPIs for resident VPEs and wake non-resident VPEs when required. * Emulation of the GICv5 IRS MMIO CONFIG_FRAME for guests. Virtualisation, MPAM, MEC, and SWERR are not supported and are RAZ/WI. * SPI injection support using GIC VDPEND. Once injected, the GICv5 hardware manages the SPI lifecycle. * Save/restore support for GICv5 EL1 system registers, IRS MMIO state, and guest ISTs. SPI and LPI IST state is transferred through userspace-owned buffers using KVM_DEV_ARM_VGIC_GRP_IST. * Documentation for the new VGICv5 IRS userspace interfaces and the required save/restore ordering. * Selftests for the UAPI components, the PPI, SPI, and LPI support, and save/restore. This series keeps SPI, LPI, and save/restore support together intentionally. SPI and LPI support are needed to run realistic guests, while the save/restore interface is included at the same time so that the new userspace ABI is complete from the point it is exposed: userspace should not be able to create VGICv5 state that it cannot also migrate. The IST migration selftest restores state into a separate VM, re-saves the SPI and LPI IST images before the destination runs, and compares them byte-for-byte with the source images. It also validates restored IRS MMIO state through SPI/LPI delivery, priority, enable, and affinity behavior. LPIs are explicitly driven by the guest through the IRS/IST state. This series does not add direct LPI injection support, MSI support, or GICv5 ITS emulation. These changes are based on v7.2-rc6. I've pushed the full set of changes to a branch at [6]. Changes since v4 [7]: * Rebased onto v7.2-rc6 and addressed review feedback from Marc and Fuad, together with the Sashiko AI reports for v4. Thanks all! * Aligned ACPI maintenance-interrupt discovery with GICv3. Broken MADT descriptions now produce FW_BUG warnings rather than preventing KVM initialisation, and the interrupt is always registered as level-sensitive. * Reworked host IRS capability discovery to cache raw IRS_IDR2, IRS_IDR3, and IRS_IDR4 values and derive their fields through accessors. This avoids tying future EL2 code to the decoded layout of kvm_vgic_global_state. * Hardened hardware-shared table handling for non-coherent IRS implementations. IRS operations and CPU table accesses now share a lock, VPET, VMD and VPED allocations are rounded up to whole cache lines, descriptors are initialised before publication, and VMT configuration waits for the IRS to become idle. * Fixed sparse vCPU ID handling. The VPET and architectural VPE ID now use the userspace-provided vcpu_id, while doorbells and VPED storage use the dense internal vcpu_idx. IDs outside the available VPE ID space are rejected. * Limited virtual GICv5 implementations to 1024 SPIs so that the physically contiguous per-SPI state allocation remains within KMALLOC_MAX_SIZE. The common IRQ routing table accommodates 1024 pins, while route validation retains the existing 988-pin limit for GICv2 and GICv3. * Tightened LPI IST lifetime and migration rules. Guest Valid-to-Valid IRS_IST_BASER writes can no longer change the address, and once a host LPI IST exists, userspace may replay but not alter IRS_IST_BASER or IRS_IST_CFGR. LPI IST saves also require the VMTE ID width to match IRS_IST_CFGR. The IST migration descriptor has moved into the arm64-specific UAPI header. * Hardened IRS and doorbell operation. GICv5 probing now fails without a host LPI domain, commands require a valid doorbell IRQ, running vCPUs are reloaded only on IRSEN transitions, and WFI doorbells are requested only while the virtual IRS is enabled. * The resident, non-resident, and VDPEND nVHE handlers are explicit no-ops under pKVM. This matches the fix by Fuad for the already-upstreamed GICv5 hypercalls [8]. * Expanded the selftests to cover the 1024-SPI boundary, live IST register restrictions, sparse vCPU IDs, and rejection of vCPU IDs outside the GICv5 VPE ID space. Thanks for taking the time to look at these changes! Thanks, Sascha [1] https://lore.kernel.org/all/20260319154937.3619520-1-sascha.bischoff@ar= m.com/ [2] https://developer.arm.com/documentation/aes0070/latest [3] https://developer.arm.com/documentation/108086/latest [4] https://linaro.atlassian.net/wiki/x/CQAF-wY [5] https://lore.kernel.org/all/20260116182606.61856-1-sascha.bischoff@arm.= com/ [6] https://gitlab.arm.com/linux-arm/linux-sb/-/tree/gicv5_kvm_irs_support_= v5 [7] https://lore.kernel.org/all/20260724104819.1296803-1-sascha.bischoff@ar= m.com/ [8] https://lore.kernel.org/all/20260806100256.371164-1-fuad.tabba@linux.de= v/ Sascha Bischoff (49): irqchip/gic-v5: Allow KVM setup without a maintenance IRQ irqchip/gic-v5: Provide OF IRS config frame attrs to KVM irqchip/gic-v5: Set up gic_kvm_info on ACPI hosts KVM: arm64: gic-v5: Define remaining IRS MMIO registers arm64/sysreg: Add GICv5 GIC VDPEND encoding arm64/sysreg: Update ICC_CR0_EL1 with LINK and LINK_IDLE fields KVM: arm64: gic-v5: Cache host IRS ID registers KVM: arm64: gic-v5: Add VPE doorbell domain KVM: arm64: gic-v5: Create and manage VM and VPE tables KVM: arm64: gic-v5: Introduce guest IST alloc and management KVM: arm64: gic-v5: Implement VMT/vIST IRS MMIO Ops KVM: arm64: gic-v5: Keep GICv5 vCPU limit model-specific KVM: arm64: gic-v5: Implement VPE IRS MMIO Ops KVM: arm64: gic-v5: Set up VMTEs and VPE doorbells KVM: arm64: gic-v5: Add resident/non-resident hyp calls KVM: arm64: gic-v5: Request doorbells when VPEs enter WFI KVM: arm64: gic-v5: Introduce struct vgic_v5_irs and IRS base address KVM: arm64: gic-v5: Add IRS IODEV support to MMIO handlers KVM: arm64: gic-v5: Add KVM_VGIC_V5_ADDR_TYPE_IRS to UAPI KVM: arm64: gic-v5: Add GICv5 IRS IODEV and MMIO emulation KVM: arm64: gic-v5: Initialise per-VM IRS state KVM: arm64: gic-v5: Register the IRS IODEV KVM: arm64: gic-v5: Set IRICHPPIDIS based on IRS enable state KVM: arm64: selftests: Update vGICv5 selftest to set IRS address KVM: arm64: gic-v5: Add GIC VDPEND hyp call KVM: arm64: gic: Introduce set_pending_state() to irq_ops KVM: arm64: gic-v5: Support SPI injection Documentation: KVM: Extend VGICv5 device attribute docs KVM: arm64: gic-v5: Add GICv5 SPI injection to irqfd KVM: arm64: gic-v5: Mask per-vCPU PPI state in vgic_v5_finalize_ppi_state() KVM: arm64: gic-v5: Add GICv5 EL1 sysreg userspace accessors KVM: arm64: gic-v5: Handle userspace accesses to IRS MMIO region KVM: arm64: gic-v5: Add CoreSight MMIO regs to IRS KVM: arm64: gic-v5: Add VGICv5 IST save/restore UAPI KVM: arm64: gic-v5: Implement save/restore mechanisms for ISTs Documentation: KVM: Document KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS for VGICv5 Documentation: KVM: Add KVM_DEV_ARM_VGIC_GRP_IRS_REGS to VGICv5 docs Documentation: KVM: Add docs for KVM_DEV_ARM_VGIC_GRP_IST Documentation: KVM: Add the VGICv5 IRS save/restore sequences KVM: selftests: Add VGICv5 IRS address attribute tests KVM: selftests: Add VGICv5 NR_IRQS attribute tests KVM: selftests: Add VGICv5 IRS_REGS attribute tests KVM: selftests: Add VGICv5 IST attribute tests KVM: selftests: Add VGICv5 USERSPACE_PPIS tests KVM: selftests: Add VGICv5 CPU sysreg attribute tests KVM: selftests: Add VGICv5 SPI injection tests KVM: selftests: Add VGICv5 LPI delivery tests KVM: selftests: Add VGICv5 IST save/restore coverage KVM: selftests: Add VGICv5 sparse vCPU IDs test Documentation/virt/kvm/api.rst | 3 +- .../virt/kvm/devices/arm-vgic-v5.rst | 271 ++- arch/arm64/include/asm/kvm_asm.h | 3 + arch/arm64/include/asm/kvm_host.h | 1 + arch/arm64/include/asm/kvm_hyp.h | 3 + arch/arm64/include/asm/sysreg.h | 13 +- arch/arm64/include/uapi/asm/kvm.h | 15 + arch/arm64/kvm/Makefile | 3 +- arch/arm64/kvm/arm.c | 10 +- arch/arm64/kvm/hyp/nvhe/hyp-main.c | 35 + arch/arm64/kvm/hyp/vgic-v5-sr.c | 45 + arch/arm64/kvm/sys_regs.c | 6 +- arch/arm64/kvm/vgic-sys-reg-v5.c | 519 +++++ arch/arm64/kvm/vgic/vgic-init.c | 150 +- arch/arm64/kvm/vgic/vgic-irqfd.c | 18 +- arch/arm64/kvm/vgic/vgic-irs-v5.c | 1184 ++++++++++ arch/arm64/kvm/vgic/vgic-kvm-device.c | 270 ++- arch/arm64/kvm/vgic/vgic-mmio.c | 6 + arch/arm64/kvm/vgic/vgic-mmio.h | 2 + arch/arm64/kvm/vgic/vgic-v5-tables.c | 1860 ++++++++++++++++ arch/arm64/kvm/vgic/vgic-v5-tables.h | 140 ++ arch/arm64/kvm/vgic/vgic-v5.c | 1139 +++++++++- arch/arm64/kvm/vgic/vgic.c | 37 +- arch/arm64/kvm/vgic/vgic.h | 21 + arch/arm64/tools/sysreg | 4 +- drivers/irqchip/irq-gic-v5-irs.c | 19 +- drivers/irqchip/irq-gic-v5.c | 112 +- include/kvm/arm_vgic.h | 210 +- include/linux/irqchip/arm-gic-v5.h | 256 ++- include/linux/irqchip/arm-vgic-info.h | 5 + tools/arch/arm64/include/uapi/asm/kvm.h | 15 + tools/testing/selftests/kvm/arm64/vgic_v5.c | 1931 ++++++++++++++++- .../selftests/kvm/include/arm64/gic_v5.h | 105 + 33 files changed, 8208 insertions(+), 203 deletions(-) create mode 100644 arch/arm64/kvm/vgic-sys-reg-v5.c create mode 100644 arch/arm64/kvm/vgic/vgic-irs-v5.c create mode 100644 arch/arm64/kvm/vgic/vgic-v5-tables.c create mode 100644 arch/arm64/kvm/vgic/vgic-v5-tables.h --=20 2.34.1