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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 3ICer6NG2N6LpVOSXWWl2vSWGuzhgNZSNqUPpHU9iBKzhymKm//dgrWHznp+mmJJ16dkh60GosJrHcBzLe+H3KPXMaDwK1XMPP32ckggQGEg30L9WWc797nzUQPjlI4tx+H6SmNQ6E4l5sDig0Z+Ua1f1UEY9Lwry361g+v7GDhg6vOlHvF+y1FpsTdb9kar/UYTS5w3tR4tXDt4ELKH70fk/js3XIoK5LpY21RfqkdlUYjQdhW/lTwghtWK0UeZAfFqW/X0KIOhSXYsk+ZsFPWg+7TIqVun4sAq0Df737Qqw+5NfBdzeqz4QqhzzYc3SLp/dN7GGer5I/qAiv2dbD/EcIEzulgSCoOmWr5cWnv0D9BDDCp2siYugRZkdPmmRdyIPWbCB6Dc4LQO09tXYJyUcnHsinydyKsIUhohUjxlBRqSmZerIS2qtDAXW0xL X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Aug 2026 11:27:24.3325 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b5e9099e-9f31-446c-381d-08def476da9e X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[4.158.2.129];Helo=[outbound-uk1.az.dlp.m.darktrace.com] X-MS-Exchange-CrossTenant-AuthSource: DU6PEPF0000B61B.eurprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DBAPR08MB5624 The VGICv5 documentation still describes the device as supporting PPIs only. Update the overview to cover PPI, SPI, and LPI interrupts. PPIs and SPIs can be injected by in-kernel devices or through KVM_IRQ_LINE, while LPI pending state is driven by the guest and handled in hardware through the LPI IST. Document the GICv5 IRS address attribute and its GPA layout requirements. The IRS region must be 64K aligned and covers a 128K range. Also document the GICv5-specific interpretation of KVM_DEV_ARM_VGIC_GRP_NR_IRQS. Unlike GICv2 and GICv3, the value describes only the number of SPIs exposed by the IRS and does not include SGIs or PPIs. The supported range is 32 through 1024 SPIs in multiples of 32, and defaults to 32 when userspace leaves it unset. Signed-off-by: Sascha Bischoff --- .../virt/kvm/devices/arm-vgic-v5.rst | 35 ++++++++++++++++--- 1 file changed, 31 insertions(+), 4 deletions(-) diff --git a/Documentation/virt/kvm/devices/arm-vgic-v5.rst b/Documentation= /virt/kvm/devices/arm-vgic-v5.rst index 70b9162755c7e..c782ea4d4609c 100644 --- a/Documentation/virt/kvm/devices/arm-vgic-v5.rst +++ b/Documentation/virt/kvm/devices/arm-vgic-v5.rst @@ -12,12 +12,39 @@ Only one VGIC instance may be instantiated through this= API. The created VGIC will act as the VM interrupt controller, requiring emulated user-space dev= ices to inject interrupts to the VGIC instead of directly to CPUs. =20 -Creating a guest GICv5 device requires a GICv5 host. The current VGICv5 d= evice -only supports PPI interrupts. These can either be injected from emulated -in-kernel devices (such as the Arch Timer, or PMU), or via the KVM_IRQ_LIN= E -ioctl. +Creating a guest GICv5 device requires a GICv5 host. The VGICv5 device su= pports +PPI, SPI, and LPI interrupts. The PPI and SPI interrupts can either be in= jected +from emulated in-kernel devices (such as the Arch Timer, or PMU), or via t= he +KVM_IRQ_LINE ioctl. LPIs are not externally injected, but are handled in +hardware via the LPI IST. Their pending state is driven directly by the g= uest. =20 Groups: + KVM_DEV_ARM_VGIC_GRP_ADDR + Attributes: + + KVM_VGIC_V5_ADDR_TYPE_IRS (rw, 64-bit) + Base address in the guest physical address space of the GICv5 IRS + (Interrupt Routing Service) register mappings. Only valid for + KVM_DEV_TYPE_ARM_VGIC_V5. This address needs to be 64K aligned and = the + region covers 128 KByte - the IRS has a CONFIG_FRAME and a SETLPI_FR= AME, + each of which is 64 KBytes in size. + + Setting the address of the IRS in GPA space is mandatory before VGIC + resources are mapped, as the IRS is responsible for handling SPIs an= d + LPIs. Failure to set the IRS address before the first vCPU run resul= ts in + an error. + + KVM_DEV_ARM_VGIC_GRP_NR_IRQS + Attributes: + + A value describing the number of SPIs for this GIC instance. This is + GICv5-specific: unlike GICv2/v3, the value does not include SGIs or PP= Is. + The value ranges from 32 to KVM's VGICv5 maximum of 1024 SPIs, in + increments of 32. If userspace does not set this attribute, KVM uses 3= 2 + SPIs by default. + + kvm_device_attr.addr points to a __u32 value. + KVM_DEV_ARM_VGIC_GRP_CTRL Attributes: =20 --=20 2.34.1