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From: sashiko-bot@kernel.org
To: "Sascha Bischoff" <Sascha.Bischoff@arm.com>
Cc: kvmarm@lists.linux.dev, "Marc Zyngier" <maz@kernel.org>,
	"Oliver Upton" <oupton@kernel.org>,
	kvm@vger.kernel.org
Subject: Re: [PATCH 5/5] KVM: arm64: vgic: Reject out-of-range GICv5 PPI IDs
Date: Mon, 10 Aug 2026 11:16:14 +0000	[thread overview]
Message-ID: <20260810111614.DDC731F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260810102652.758719-6-sascha.bischoff@arm.com>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Critical] Returning NULL for out-of-range GICv5 PPIs causes a deterministic host kernel panic via NULL pointer dereference or BUG_ON() during timer initialization with user-controlled inputs.
--

--- Patch [5]: [PATCH 5/5] KVM: arm64: vgic: Reject out-of-range GICv5 PPI IDs ---
commit b745364de86ed8f379d9297c2d334e7a734654d6
Author: Sascha Bischoff <Sascha.Bischoff@arm.com>

KVM: arm64: vgic: Reject out-of-range GICv5 PPI IDs

The commit prevents KVM from clamping out-of-range GICv5 PPIs to index 0.
It introduces a check in vgic_get_vcpu_irq() that returns NULL when the
extracted hardware IRQ ID exceeds the supported range.

Link: https://sashiko.dev/#/patchset/20260724104819.1296803-1-sascha.bischoff@arm.com?part=27

> diff --git a/arch/arm64/kvm/vgic/vgic.c b/arch/arm64/kvm/vgic/vgic.c
> index 3077cfdaa146d..d0c91f0c52698 100644
> --- a/arch/arm64/kvm/vgic/vgic.c
> +++ b/arch/arm64/kvm/vgic/vgic.c
> @@ -118,6 +118,8 @@ struct vgic_irq *vgic_get_vcpu_irq(struct kvm_vcpu *vcpu, u32 intid)
>  		switch (type) {
>  		case KVM_DEV_TYPE_ARM_VGIC_V5:
>  			intid = vgic_v5_get_hwirq_id(intid);
> +			if (intid >= VGIC_V5_NR_PRIVATE_IRQS)
> +				return NULL;

[Severity: Critical]
Does returning NULL here allow a malicious userspace process to trigger a host
kernel panic?

If a user configures a VM and sets the timer IRQ to an out-of-bounds GICv5 PPI
ID (>= 64) via the KVM_SET_DEVICE_ATTR ioctl, the input is validated using
irq_is_ppi(). Because irq_is_ppi() only checks the upper type bits for GICv5,
it accepts the invalid ID and stores it.

When the vCPU is subsequently run, kvm_timer_enable() initializes the timers
and calls functions like kvm_vgic_set_owner() and kvm_vgic_map_phys_irq() with
the out-of-bounds IRQ. These callers lack NULL checks and assume the returned
pointer is valid.

For example, kvm_vgic_set_owner() unconditionally dereferences it:

arch/arm64/kvm/vgic/vgic.c:kvm_vgic_set_owner() {
	irq = vgic_get_vcpu_irq(vcpu, intid);
	raw_spin_lock_irqsave(&irq->irq_lock, flags);
	...
}

And kvm_vgic_map_phys_irq() explicitly asserts it with BUG_ON():

arch/arm64/kvm/vgic/vgic.c:kvm_vgic_map_phys_irq() {
	struct vgic_irq *irq = vgic_get_vcpu_irq(vcpu, vintid);
	...
	BUG_ON(!irq);
	...
}

Should the boundary check be enforced earlier, such as during the ioctl
validation itself, to prevent storing the invalid ID and crashing during
timer initialization?

>  			intid = array_index_nospec(intid, VGIC_V5_NR_PRIVATE_IRQS);
>  			break;
>  		default:

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260810102652.758719-1-sascha.bischoff@arm.com?part=5

      reply	other threads:[~2026-08-10 11:16 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-08-10 10:27 [PATCH 0/5] arm64: gic-v5: Fixes from GICv5 KVM IRS review Sascha Bischoff
2026-08-10 10:27 ` [PATCH 1/5] KVM: arm64: vgic: Free gic_kvm_info on initialization failure Sascha Bischoff
2026-08-10 10:28 ` [PATCH 2/5] irqchip/gic-v5: Clear per-CPU IRS data on teardown Sascha Bischoff
2026-08-10 10:47   ` sashiko-bot
2026-08-10 11:45     ` Lorenzo Pieralisi
2026-08-10 11:36   ` Lorenzo Pieralisi
2026-08-10 10:28 ` [PATCH 3/5] irqchip/gic-v5: Synchronize CPU interface disable Sascha Bischoff
2026-08-10 10:54   ` sashiko-bot
2026-08-10 10:29 ` [PATCH 4/5] KVM: arm64: vgic: Prevent speculative SPI array underflow Sascha Bischoff
2026-08-10 10:29 ` [PATCH 5/5] KVM: arm64: vgic: Reject out-of-range GICv5 PPI IDs Sascha Bischoff
2026-08-10 11:16   ` sashiko-bot [this message]

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