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From: Alex Williamson <alex@shazbot.org>
To: <mhonap@nvidia.com>
Cc: <jgg@ziepe.ca>, <ankita@nvidia.com>, <jic23@kernel.org>,
	<dave.jiang@intel.com>, <alejandro.lucero-palau@amd.com>,
	<smadhavan@nvidia.com>, <corbet@lwn.net>,
	<skhan@linuxfoundation.org>, <dave@stgolabs.net>,
	<alison.schofield@intel.com>, <vishal.l.verma@intel.com>,
	<iweiny@kernel.org>, <ming.li@zohomail.com>, <yishaih@nvidia.com>,
	<skolothumtho@nvidia.com>, <kevin.tian@intel.com>,
	<bhelgaas@google.com>, <dmatlack@google.com>, <kees@kernel.org>,
	<gustavoars@kernel.org>, <cjia@nvidia.com>, <kjaju@nvidia.com>,
	<vsethi@nvidia.com>, <zhiw@nvidia.com>,
	<linux-doc@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	<kvm@vger.kernel.org>, <linux-cxl@vger.kernel.org>,
	<linux-pci@vger.kernel.org>, <linux-kselftest@vger.kernel.org>,
	<linux-hardening@vger.kernel.org>,
	alex@shazbot.org
Subject: Re: [PATCH v4 08/27] vfio/cxl: Add the vfio-cxl module skeleton
Date: Wed, 26 Aug 2026 16:50:33 -0600	[thread overview]
Message-ID: <20260826165033.582735f4@shazbot.org> (raw)
In-Reply-To: <20260813093631.2288172-9-mhonap@nvidia.com>

On Thu, 13 Aug 2026 15:06:12 +0530
<mhonap@nvidia.com> wrote:

> From: Manish Honap <mhonap@nvidia.com>
> 
> Add the vfio-cxl module that vfio-pci loads on demand for CXL Type-2
> devices. It registers a set of callbacks with vfio-pci-core at
> module_init and drops them at exit; the callbacks are stubs here and
> are filled in by later patches.
> 
> VFIO_CXL depends on CXL_BUS and builds as vfio-cxl.ko, which
> request_module("vfio-cxl") resolves through MODULE_ALIAS.
> 
> Signed-off-by: Manish Honap <mhonap@nvidia.com>
> ---
>  MAINTAINERS                          |  7 +++++
>  drivers/vfio/pci/Kconfig             |  2 ++
>  drivers/vfio/pci/Makefile            |  2 ++
>  drivers/vfio/pci/cxl/Kconfig         | 11 ++++++++
>  drivers/vfio/pci/cxl/Makefile        |  3 ++
>  drivers/vfio/pci/cxl/vfio_cxl_core.c | 41 ++++++++++++++++++++++++++++
>  6 files changed, 66 insertions(+)
>  create mode 100644 drivers/vfio/pci/cxl/Kconfig
>  create mode 100644 drivers/vfio/pci/cxl/Makefile
>  create mode 100644 drivers/vfio/pci/cxl/vfio_cxl_core.c
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index c665bf8f1a28..aa8cecbc4cf2 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -28312,6 +28312,13 @@ L:	kvm@vger.kernel.org
>  S:	Maintained
>  F:	drivers/vfio/cdx/*
>  
> +VFIO CXL DRIVER
> +M:	Manish Honap <mhonap@nvidia.com>
> +L:	kvm@vger.kernel.org
> +L:	linux-cxl@vger.kernel.org
> +S:	Supported
> +F:	drivers/vfio/pci/cxl/
> +
>  VFIO DRIVER
>  M:	Alex Williamson <alex@shazbot.org>
>  L:	kvm@vger.kernel.org
> diff --git a/drivers/vfio/pci/Kconfig b/drivers/vfio/pci/Kconfig
> index 296bf01e185e..c3f54fc8ccc0 100644
> --- a/drivers/vfio/pci/Kconfig
> +++ b/drivers/vfio/pci/Kconfig
> @@ -70,6 +70,8 @@ source "drivers/vfio/pci/virtio/Kconfig"
>  
>  source "drivers/vfio/pci/nvgrace-gpu/Kconfig"
>  
> +source "drivers/vfio/pci/cxl/Kconfig"
> +
>  source "drivers/vfio/pci/qat/Kconfig"
>  
>  source "drivers/vfio/pci/xe/Kconfig"

It seems fair to put this above the variant driver Kconfigs rather than
bury it among them.

> diff --git a/drivers/vfio/pci/Makefile b/drivers/vfio/pci/Makefile
> index 6138f1bf241d..c3031070a1f3 100644
> --- a/drivers/vfio/pci/Makefile
> +++ b/drivers/vfio/pci/Makefile
> @@ -21,6 +21,8 @@ obj-$(CONFIG_VIRTIO_VFIO_PCI) += virtio/
>  
>  obj-$(CONFIG_NVGRACE_GPU_VFIO_PCI) += nvgrace-gpu/
>  
> +obj-$(CONFIG_VFIO_CXL) += cxl/
> +
>  obj-$(CONFIG_QAT_VFIO_PCI) += qat/
>  
>  obj-$(CONFIG_XE_VFIO_PCI) += xe/

Here again, cxl is a feature of vfio-pci-core.  I'd promote it to
between vfio-pci-core and vfio-pci.  The earlier linking also has the
benefit that in the typical case it will be available before the
builtin drivers (but keep the deferred loading behavior).  Thanks,

Alex

> diff --git a/drivers/vfio/pci/cxl/Kconfig b/drivers/vfio/pci/cxl/Kconfig
> new file mode 100644
> index 000000000000..1392fa4ed15d
> --- /dev/null
> +++ b/drivers/vfio/pci/cxl/Kconfig
> @@ -0,0 +1,11 @@
> +# SPDX-License-Identifier: GPL-2.0-only
> +config VFIO_CXL
> +	tristate "VFIO support for CXL Type-2 devices"
> +	depends on CXL_BUS && CXL_MEM
> +	select VFIO_PCI_CORE
> +	help
> +	  Add CXL HDM handling to vfio-pci so a CXL Type-2 device, such as a
> +	  CXL-attached accelerator, can be assigned to a virtual machine.
> +	  vfio-pci loads this module on demand when it binds a CXL device.
> +
> +	  If you don't know what to do here, say N.
> diff --git a/drivers/vfio/pci/cxl/Makefile b/drivers/vfio/pci/cxl/Makefile
> new file mode 100644
> index 000000000000..8501bf626108
> --- /dev/null
> +++ b/drivers/vfio/pci/cxl/Makefile
> @@ -0,0 +1,3 @@
> +# SPDX-License-Identifier: GPL-2.0-only
> +obj-$(CONFIG_VFIO_CXL) += vfio-cxl.o
> +vfio-cxl-y := vfio_cxl_core.o
> diff --git a/drivers/vfio/pci/cxl/vfio_cxl_core.c b/drivers/vfio/pci/cxl/vfio_cxl_core.c
> new file mode 100644
> index 000000000000..cbec7319452c
> --- /dev/null
> +++ b/drivers/vfio/pci/cxl/vfio_cxl_core.c
> @@ -0,0 +1,41 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * VFIO support for CXL Type-2 devices.
> + *
> + * Copyright (c) 2026 NVIDIA Corporation & Affiliates
> + */
> +
> +#include <linux/module.h>
> +#include <linux/vfio_pci_core.h>
> +
> +static int vfio_cxl_init_device(struct vfio_pci_core_device *vdev)
> +{
> +	return 0;
> +}
> +
> +static void vfio_cxl_release_device(struct vfio_pci_core_device *vdev)
> +{
> +}
> +
> +static const struct vfio_cxl_ops vfio_cxl_ops = {
> +	.init_device	= vfio_cxl_init_device,
> +	.release_device	= vfio_cxl_release_device,
> +	.owner		= THIS_MODULE,
> +};
> +
> +static int __init vfio_cxl_init(void)
> +{
> +	return vfio_pci_core_register_cxl_ops(&vfio_cxl_ops);
> +}
> +
> +static void __exit vfio_cxl_exit(void)
> +{
> +	vfio_pci_core_unregister_cxl_ops(&vfio_cxl_ops);
> +}
> +
> +module_init(vfio_cxl_init);
> +module_exit(vfio_cxl_exit);
> +
> +MODULE_LICENSE("GPL");
> +MODULE_DESCRIPTION("VFIO support for CXL Type-2 devices");
> +MODULE_ALIAS("vfio-cxl");


  reply	other threads:[~2026-08-26 22:50 UTC|newest]

Thread overview: 38+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-08-13  9:36 [PATCH v4 00/27] vfio/pci: Add CXL Type-2 device passthrough support mhonap
2026-08-13  9:36 ` [PATCH v4 01/27] cxl: Fix resource.c include path and export cxl_restore_hdm_after_pci_reset mhonap
2026-08-21 22:52   ` Jonathan Cameron
2026-08-22  1:22     ` Manish Honap
2026-08-13  9:36 ` [PATCH v4 02/27] cxl/regs: Skip sub-block region request for BAR-owning drivers mhonap
2026-08-25 21:26   ` Alex Williamson
2026-08-13  9:36 ` [PATCH v4 03/27] cxl: Move component register defines to uapi/cxl/cxl_regs.h mhonap
2026-08-13  9:36 ` [PATCH v4 04/27] cxl: Establish media readiness in cxl_mem_probe() mhonap
2026-08-25 22:18   ` Alex Williamson
2026-08-13  9:36 ` [PATCH v4 05/27] cxl: Add a function-scoped reset entry for vfio-pci mhonap
2026-08-25 23:11   ` Alex Williamson
2026-08-13  9:36 ` [PATCH v4 06/27] vfio/pci: Add CXL ops registration interface mhonap
2026-08-26 21:11   ` Alex Williamson
2026-08-13  9:36 ` [PATCH v4 07/27] vfio/pci: Detect CXL devices and load vfio-cxl on demand mhonap
2026-08-26 22:17   ` Alex Williamson
2026-08-13  9:36 ` [PATCH v4 08/27] vfio/cxl: Add the vfio-cxl module skeleton mhonap
2026-08-26 22:50   ` Alex Williamson [this message]
2026-08-13  9:36 ` [PATCH v4 09/27] vfio/cxl: Create the CXL memory device at bind mhonap
2026-08-13  9:36 ` [PATCH v4 10/27] vfio/cxl: Reject unsupported decoder topologies " mhonap
2026-08-13  9:36 ` [PATCH v4 11/27] vfio/cxl: Own the whole component register BAR mhonap
2026-08-13  9:36 ` [PATCH v4 12/27] vfio/pci: Let a provider exclude a BAR sub-range from mmap mhonap
2026-08-13  9:36 ` [PATCH v4 13/27] vfio/pci: Refuse read/write to an excluded BAR sub-range mhonap
2026-08-13  9:36 ` [PATCH v4 14/27] vfio: Add CXL region type for the HDM region mhonap
2026-08-13  9:36 ` [PATCH v4 15/27] vfio/pci: Call CXL open and close hooks around device use mhonap
2026-08-13  9:36 ` [PATCH v4 16/27] vfio/cxl: Shadow the CXL DVSEC body at open mhonap
2026-08-13  9:36 ` [PATCH v4 17/27] vfio/cxl: Virtualize the CXL DVSEC mhonap
2026-08-13  9:36 ` [PATCH v4 18/27] vfio/cxl: Expose the HDM memory and trap the decoder registers mhonap
2026-08-13  9:36 ` [PATCH v4 19/27] vfio/cxl: Keep the HDM decoder block off the direct BAR mapping mhonap
2026-08-13  9:36 ` [PATCH v4 20/27] vfio/cxl: Emulate the HDM decoder commit handshake mhonap
2026-08-13  9:36 ` [PATCH v4 21/27] vfio/cxl: Describe the CXL device and decoder geometry to userspace mhonap
2026-08-13  9:36 ` [PATCH v4 22/27] vfio/cxl: Revoke the HDM mapping on reset and power transitions mhonap
2026-08-13  9:36 ` [PATCH v4 23/27] vfio/cxl: Refresh the decoder snapshot after a device reset mhonap
2026-08-13  9:36 ` [PATCH v4 24/27] vfio/cxl: Service a guest-triggered CXL reset mhonap
2026-08-13  9:36 ` [PATCH v4 25/27] vfio/pci: Provide an opt-out for the CXL Type-2 extensions mhonap
2026-08-13  9:36 ` [PATCH v4 26/27] Documentation: vfio-pci: Document CXL Type-2 device passthrough mhonap
2026-08-13  9:36 ` [PATCH v4 27/27] selftests/vfio: Add CXL Type-2 passthrough corner-case tests mhonap
2026-08-26  7:28   ` Shuai Xue
2026-08-26 16:17     ` Manish Honap

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