From: Kim Phillips <kim.phillips@amd.com>
To: <linux-kernel@vger.kernel.org>, <x86@kernel.org>,
<linux-coco@lists.linux.dev>, <kvm@vger.kernel.org>
Cc: Sean Christopherson <seanjc@google.com>,
Paolo Bonzini <pbonzini@redhat.com>,
K Prateek Nayak <kprateek.nayak@amd.com>,
"Nikunj A Dadhania" <nikunj@amd.com>,
Tom Lendacky <thomas.lendacky@amd.com>,
"Michael Roth" <michael.roth@amd.com>,
Borislav Petkov <borislav.petkov@amd.com>,
Borislav Petkov <bp@alien8.de>, Naveen Rao <naveen.rao@amd.com>,
David Kaplan <david.kaplan@amd.com>,
Pawan Gupta <pawan.kumar.gupta@linux.intel.com>,
"Dave Hansen" <dave.hansen@linux.intel.com>,
Kim Phillips <kim.phillips@amd.com>,
Nathan Fontenot <nathan.fontenot@amd.com>
Subject: [PATCH v5 8/8] KVM: SEV: Add support for SNP BTB Isolation
Date: Wed, 26 Aug 2026 17:35:10 -0500 [thread overview]
Message-ID: <20260826223510.3669875-9-kim.phillips@amd.com> (raw)
In-Reply-To: <20260826223510.3669875-1-kim.phillips@amd.com>
Advertise support for BTB Isolation via SEV_VMSA_FEATURES when SNP is
enabled. BTB Isolation is an optional feature that can be enabled by the
guest to ensure its guest Branch Target Buffers (BTBs) are not affected
by any context outside that guest.
SNP-active guests may choose to enable the Branch Target Buffer
Isolation mode through SEV_FEATURES bit 7 (BTBIsolation).
Unlike the sibling features advertised here (Secure TSC, IBPB-on-Entry),
BTB Isolation is advertised unconditionally. This is deliberate, not an
oversight: the AMD64 APM (Vol. 2, Section 15.36.17 "Side-Channel
Protection") defines BTB Isolation as architecturally present on every
SEV-SNP-capable processor. There is therefore no host enumeration bit
for it (no CPUID leaf or MSR capability), by design -- unlike
IBPB-on-Entry, whose host support is enumerated via
CPUID Fn8000_001F[IbpbOnEntry] bit 31 precisely because it is not
universal. A per-feature host gate is thus neither possible nor
meaningful; if SNP is supported, BTB Isolation is present.
Nor does the guest have to take the host's word for it. SEV_FEATURES is
written into the VMSA by sev_es_sync_vmsa() and measured by
SNP_LAUNCH_UPDATE with SNP_PAGE_TYPE_VMSA, so bit 7 is covered by the
launch measurement and appears in the attestation report. At runtime the
guest can additionally read the active state from SEV_STATUS bit 9
(MSR_AMD64_SNP_BTB_ISOLATION, dumped as "BTBIsol" by
sev_status_feat_names[] in arch/x86/coco/sev/core.c). A guest requiring
BTB Isolation can therefore confirm it is active rather than trusting what
the host advertised.
Also add SVM_SEV_FEAT_BTB_ISOLATION to the sev_init2 selftest's
SNP_ONLY_FEATURES and KNOWN_FEATURES to validate it is accepted
for SNP guests and rejected for SEV-ES.
For more info, refer to page 615, Section 15.36.17 "Side-Channel
Protection", AMD64 Architecture Programmer's Manual Volume 2: System
Programming Part 2, Pub. 24593 Rev. 3.42 - March 2024 (see Link).
Link: https://bugzilla.kernel.org/attachment.cgi?id=306250
Cc: Sean Christopherson <seanjc@google.com>
Cc: Borislav Petkov (AMD) <bp@alien8.de>
Signed-off-by: Kim Phillips <kim.phillips@amd.com>
Assisted-by: ClaudeCode:claude-opus-4-7
Reviewed-by: Tom Lendacky <thomas.lendacky@amd.com>
---
arch/x86/include/asm/svm.h | 2 ++
arch/x86/kvm/svm/sev.c | 8 ++++++++
tools/testing/selftests/kvm/x86/sev_init2_tests.c | 2 ++
3 files changed, 12 insertions(+)
diff --git a/arch/x86/include/asm/svm.h b/arch/x86/include/asm/svm.h
index 9d8107824d10..0da2234b71c6 100644
--- a/arch/x86/include/asm/svm.h
+++ b/arch/x86/include/asm/svm.h
@@ -309,10 +309,12 @@ static_assert((X2AVIC_4K_MAX_PHYSICAL_ID & AVIC_PHYSICAL_MAX_INDEX_MASK) == X2AV
#define SVM_SEV_FEAT_RESTRICTED_INJECTION BIT_ULL(3)
#define SVM_SEV_FEAT_ALTERNATE_INJECTION BIT_ULL(4)
#define SVM_SEV_FEAT_DEBUG_SWAP BIT_ULL(5)
+#define SVM_SEV_FEAT_BTB_ISOLATION BIT_ULL(7)
#define SVM_SEV_FEAT_SECURE_TSC BIT_ULL(9)
#define SVM_SEV_FEAT_IBPB_ON_ENTRY BIT_ULL(21)
#define SVM_SEV_FEAT_SNP_ONLY_MASK (SVM_SEV_FEAT_SNP_ACTIVE | \
+ SVM_SEV_FEAT_BTB_ISOLATION | \
SVM_SEV_FEAT_SECURE_TSC | \
SVM_SEV_FEAT_IBPB_ON_ENTRY)
diff --git a/arch/x86/kvm/svm/sev.c b/arch/x86/kvm/svm/sev.c
index 20a761cf3491..53cc6d043883 100644
--- a/arch/x86/kvm/svm/sev.c
+++ b/arch/x86/kvm/svm/sev.c
@@ -3260,6 +3260,14 @@ void __init sev_hardware_setup(void)
if (sev_snp_enabled) {
sev_supported_vmsa_features |= SVM_SEV_FEAT_SNP_ACTIVE;
+ /*
+ * Unlike Secure TSC and IBPB-on-Entry below, BTB Isolation has
+ * no host enumeration bit to gate on: the APM defines it as
+ * architecturally present on every SEV-SNP-capable processor.
+ * If SNP is supported, BTB Isolation is available.
+ */
+ sev_supported_vmsa_features |= SVM_SEV_FEAT_BTB_ISOLATION;
+
if (tsc_khz && cpu_feature_enabled(X86_FEATURE_SNP_SECURE_TSC))
sev_supported_vmsa_features |= SVM_SEV_FEAT_SECURE_TSC;
diff --git a/tools/testing/selftests/kvm/x86/sev_init2_tests.c b/tools/testing/selftests/kvm/x86/sev_init2_tests.c
index f2f97dca3935..3f592e245a66 100644
--- a/tools/testing/selftests/kvm/x86/sev_init2_tests.c
+++ b/tools/testing/selftests/kvm/x86/sev_init2_tests.c
@@ -15,11 +15,13 @@
#define SVM_SEV_FEAT_SNP_ACTIVE BIT_ULL(0)
#define SVM_SEV_FEAT_DEBUG_SWAP BIT_ULL(5)
+#define SVM_SEV_FEAT_BTB_ISOLATION BIT_ULL(7)
#define SVM_SEV_FEAT_SECURE_TSC BIT_ULL(9)
#define SVM_SEV_FEAT_IBPB_ON_ENTRY BIT_ULL(21)
/* Features valid only for SNP guests, rejected for SEV-ES and below. */
#define SNP_ONLY_FEATURES (SVM_SEV_FEAT_SNP_ACTIVE | \
+ SVM_SEV_FEAT_BTB_ISOLATION | \
SVM_SEV_FEAT_SECURE_TSC | \
SVM_SEV_FEAT_IBPB_ON_ENTRY)
--
2.43.0
prev parent reply other threads:[~2026-08-26 22:37 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-26 22:35 [PATCH v5 0/8] Add SEV-SNP BTB Isolation and IBPB-on-Entry guest features Kim Phillips
2026-08-26 22:35 ` [PATCH v5 1/8] x86/bugs: Allow forcing Automatic IBRS with SNP active using spectre_v2=eibrs Kim Phillips
2026-08-27 4:32 ` Pawan Gupta
2026-08-26 22:35 ` [PATCH v5 2/8] x86/bugs: Allow spectre_v2=ibrs on x86 vendors other than Intel Kim Phillips
2026-08-27 4:33 ` Pawan Gupta
2026-08-26 22:35 ` [PATCH v5 3/8] KVM: SVM: Define SVM_SEV_FEAT_* flags using BIT_ULL() Kim Phillips
2026-08-26 22:35 ` [PATCH v5 4/8] KVM: selftests: sev_init2: Use BIT_ULL for VMSA feature bit definition Kim Phillips
2026-08-26 22:35 ` [PATCH v5 5/8] KVM: SEV: Disallow setting SNP-only features for non-SNP guests via a single mask Kim Phillips
2026-08-26 22:35 ` [PATCH v5 6/8] KVM: SEV: Advertise SVM_SEV_FEAT_SNP_ACTIVE Kim Phillips
2026-08-26 22:35 ` [PATCH v5 7/8] KVM: SEV: Add support for IBPB-on-Entry Kim Phillips
2026-08-26 22:35 ` Kim Phillips [this message]
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