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Thu, 27 Aug 2026 17:13:04 -0400 (EDT) Date: Thu, 27 Aug 2026 15:13:03 -0600 From: Alex Williamson To: Cc: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , alex@shazbot.org Subject: Re: [PATCH v4 11/27] vfio/cxl: Own the whole component register BAR Message-ID: <20260827151303.5b34ef3b@shazbot.org> In-Reply-To: <20260813093631.2288172-12-mhonap@nvidia.com> References: <20260813093631.2288172-1-mhonap@nvidia.com> <20260813093631.2288172-12-mhonap@nvidia.com> X-Mailer: Claws Mail 4.4.0 (GTK 3.24.52; x86_64-pc-linux-gnu) Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit On Thu, 13 Aug 2026 15:06:15 +0530 wrote: > From: Manish Honap > > devm_cxl_probe_mem() maps the component registers through the CXL core. > By default the core claims each HDM/RAS sub-block, which then collides > with the full-BAR request that vfio-pci makes when the guest opens the > device. > > Discover the component registers into the device reg_map and pass > bar_owned to cxl_pci_setup_regs(), so the core maps the sub-blocks > without claiming them and vfio-pci owns the whole BAR. > > Signed-off-by: Manish Honap > --- > drivers/vfio/pci/cxl/vfio_cxl_core.c | 11 +++++++++++ > 1 file changed, 11 insertions(+) > > diff --git a/drivers/vfio/pci/cxl/vfio_cxl_core.c b/drivers/vfio/pci/cxl/vfio_cxl_core.c > index 7edc53b25576..966b7c22a6ac 100644 > --- a/drivers/vfio/pci/cxl/vfio_cxl_core.c > +++ b/drivers/vfio/pci/cxl/vfio_cxl_core.c > @@ -10,6 +10,7 @@ > #include > #include > #include > +#include > > /** > * struct vfio_cxl_state - per-device state for a vfio-cxl device > @@ -70,6 +71,16 @@ static int vfio_cxl_init_device(struct vfio_pci_core_device *vdev) > if (!cxl) > return -ENOMEM; > > + /* > + * vfio-pci requests the whole component BAR when the guest opens the > + * device. Declare the BAR owned so the CXL core maps the HDM/RAS > + * sub-blocks without claiming them and that request does not collide. > + */ > + ret = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_COMPONENT, > + &cxl->cxlds.reg_map, true); > + if (ret) > + return ret; > + > ret = cxl_set_capacity(&cxl->cxlds, hdm_size); > if (ret) > return ret; Previous comments on patch 2 suggest a different interface here, but do note that cxl_pci_set_regs() can return -EPROBE_DEFER and if we do actually want to defer the probe (until when?) we'd need to split this errno out as a legitimate probe error case versus the fallback mechanism for other errnos. Thanks, Alex