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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: Ko42Wnl0ENzfjjp77Mv0+zKVYRtxKJLz+vtjOZKMc9N8cGYdiWFLZQXc8e/7llfzWipOlM0pulU8lfdmyMWy6ApSRUo3cRNjbu7+eziwuw4ARXxziIT96Z/EdNbWPdcOJERPUmXQ9Nd/oEcS+vRl9qANVOARP9UBKj+YWRh2WNwoMpGZDilblgIYy+wr4okZlsW43m/CzEQzddpxMEPruAKKU8qO4tDTiuzpfmZJVvP6Dm4jafvisuAx3Eu0+axDGsFYzYLjQzzT2ZBXOw3GRvGEGEjDp2FNUSmTA88xnC6rVKWJpzFkd2aaX8NQiXRq29rBtOOJJKJ/T/0ikDIldeQb8f9kAZrtvLppkjYj27go7pRvrw9zqr4zuk4PgKFnet958h+YpWldyGFljj3RYuk29tkO7fo1AY7s7cLZUEZPamhWWmSZk6z170Wt2kDX X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Sep 2026 11:34:53.8202 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 60388ccd-ecaa-4942-1208-08df0a788a1c X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[4.158.2.129];Helo=[outbound-uk1.az.dlp.m.darktrace.com] X-MS-Exchange-CrossTenant-AuthSource: AMS0EPF00000197.eurprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AMBPR08MB11617 Hi all, This series builds on the initial vGICv5 support [1] and adds support for the GICv5 IRS, as described by the GICv5 (EAC0) specification [2]. With this, a GICv5 guest is no longer restricted to PPIs, and can make use of SPIs and LPIs as well. With SPIs and LPIs available, this series makes it possible to boot a full Linux guest on the Arm FVP model [3], using the setup described in Lorenzo's GICv5 Linux software enablement guide [4]. In addition, GICv5 IPIs are typically implemented as LPIs, so LPI support is what makes guests with more than one vCPU possible. The corresponding kvmtool changes are available separately [5]. With these changes, `--irqchip=3Dgicv5` works now. The `--irqchip=3Dgicv5-its` configuration does not work with this series, as ITS/MSI support is not included here. The IRS is created as part of the vgic-v5 device, and is not a separate KVM device. This is because implementing the CPU interface alone would limit a guest to a single vCPU and PPIs only. Hence, the IRS is bundled into the VGIC, much like the distributor for GICv3. The series adds the host-side plumbing needed for KVM to interact with the physical IRS, including VM and VPE table management, VPE residency, and VPE doorbells. It also adds an emulated IRS MMIO interface for the guest, together with the UAPI needed for userspace to configure the IRS address and to save/restore the IRS and IST state. The main pieces are: * Host IRS capability discovery and configuration frame plumbing. * Allocation and management of the GICv5 VM table, VPE table, VMTEs, VPEs, and host-backed guest IST storage. * VPE residency and doorbell handling, allowing the IRS to select SPIs and LPIs for resident VPEs and wake non-resident VPEs when required. * Emulation of the GICv5 IRS MMIO CONFIG_FRAME for guests. Virtualisation, MPAM, MEC, and SWERR are not supported and are RAZ/WI. * SPI injection support using GIC VDPEND. Once injected, the GICv5 hardware manages the SPI lifecycle. * Save/restore support for GICv5 EL1 system registers, IRS MMIO state, and guest ISTs. SPI and LPI IST state is transferred through userspace-owned buffers using KVM_DEV_ARM_VGIC_GRP_IST. * Documentation for the new VGICv5 IRS userspace interfaces and the required save/restore ordering. * Selftests for the UAPI components, the PPI, SPI, and LPI support, and save/restore. This series keeps SPI, LPI, and save/restore support together intentionally. SPI and LPI support are needed to run realistic guests, while the save/restore interface is included at the same time so that the new userspace ABI is complete from the point it is exposed: userspace should not be able to create VGICv5 state that it cannot also migrate. The IST migration selftest restores state into a separate VM, re-saves the SPI and LPI IST images before the destination runs, and compares them byte-for-byte with the source images. It also validates restored IRS MMIO state through SPI/LPI delivery, priority, enable, and affinity behaviour. LPIs are explicitly driven by the guest through the IRS/IST state. This series does not add direct LPI injection support, MSI support, or GICv5 ITS emulation. KVM_IRQFD_FLAG_RESAMPLE is also not supported, as the state of in-flight SPIs is fully tracked in hardware. These changes are based on v7.3-rc1. I've pushed the full set of changes to a branch at [6]. Changes since v5 [7]: * Rebased onto v7.3-rc1 and addressed the Sashiko reports for v5. * Hardened IRS command and teardown failure handling. VIST assignment timeouts now retain potentially hardware-owned memory and mark the VM dead, while teardown stops if the VPE table cannot be cleared. * Generalised model-specific vCPU ID validation across VGIC models, covering both the GICv2 ID limit and the GICv5 VPE ID limit regardless of vCPU creation order. * Added support for architecturally permitted 32-bit accesses to 64-bit IRS registers, including correct merging of partial IRS_IST_BASER writes. * Tightened LPI IST restore ordering. Restoring IRS_IST_BASER.Valid now prevents the guest from running until userspace has restored the host LPI IST, and IST snapshots are completed before checking quiescence. * Made doorbell affinity updates best-effort and tightened resource cleanup when ACPI discovery or default IRQ routing setup fails. * Expanded the selftests to cover symmetric IST descriptor validation, preserve unrelated IRS ID register fields during invalid-state tests, and avoid assumptions about the host VPE ID width. I shall be out of office from 9 September until 4 October, so my responses will be delayed during this period. Thanks for taking the time to look at these changes! Thanks, Sascha [1] https://lore.kernel.org/all/20260319154937.3619520-1-sascha.bischoff@ar= m.com/ [2] https://developer.arm.com/documentation/aes0070/latest [3] https://developer.arm.com/documentation/108086/latest [4] https://linaro.atlassian.net/wiki/x/CQAF-wY [5] https://lore.kernel.org/all/20260116182606.61856-1-sascha.bischoff@arm.= com/ [6] https://gitlab.arm.com/linux-arm/linux-sb/-/tree/gicv5_kvm_irs_support_= v6 [7] https://lore.kernel.org/all/20260807111159.429128-1-sascha.bischoff@arm= .com/ Sascha Bischoff (49): irqchip/gic-v5: Allow KVM setup without a maintenance IRQ irqchip/gic-v5: Provide OF IRS config frame attrs to KVM irqchip/gic-v5: Set up gic_kvm_info on ACPI hosts KVM: arm64: gic-v5: Define remaining IRS MMIO registers arm64/sysreg: Add GICv5 GIC VDPEND encoding arm64/sysreg: Update ICC_CR0_EL1 with LINK and LINK_IDLE fields KVM: arm64: gic-v5: Cache host IRS ID registers KVM: arm64: gic-v5: Add VPE doorbell domain KVM: arm64: gic-v5: Create and manage VM and VPE tables KVM: arm64: gic-v5: Introduce guest IST alloc and management KVM: arm64: gic-v5: Implement VMT/vIST IRS MMIO Ops KVM: arm64: vgic: Enforce model-specific vCPU limits KVM: arm64: gic-v5: Implement VPE IRS MMIO Ops KVM: arm64: gic-v5: Set up VMTEs and VPE doorbells KVM: arm64: gic-v5: Add resident/non-resident hyp calls KVM: arm64: gic-v5: Request doorbells when VPEs enter WFI KVM: arm64: gic-v5: Introduce struct vgic_v5_irs and IRS base address KVM: arm64: gic-v5: Add IRS IODEV support to MMIO handlers KVM: arm64: gic-v5: Add KVM_VGIC_V5_ADDR_TYPE_IRS to UAPI KVM: arm64: gic-v5: Add GICv5 IRS IODEV and MMIO emulation KVM: arm64: gic-v5: Initialise per-VM IRS state KVM: arm64: gic-v5: Register the IRS IODEV KVM: arm64: gic-v5: Set IRICHPPIDIS based on IRS enable state KVM: arm64: selftests: Update vGICv5 selftest to set IRS address KVM: arm64: gic-v5: Add GIC VDPEND hyp call KVM: arm64: gic: Introduce set_pending_state() to irq_ops KVM: arm64: gic-v5: Support SPI injection Documentation: KVM: Extend VGICv5 device attribute docs KVM: arm64: gic-v5: Add GICv5 SPI injection to irqfd KVM: arm64: gic-v5: Mask per-vCPU PPI state in vgic_v5_finalize_ppi_state() KVM: arm64: gic-v5: Add GICv5 EL1 sysreg userspace accessors KVM: arm64: gic-v5: Handle userspace accesses to IRS MMIO region KVM: arm64: gic-v5: Add CoreSight MMIO regs to IRS KVM: arm64: gic-v5: Add VGICv5 IST save/restore UAPI KVM: arm64: gic-v5: Implement save/restore mechanisms for ISTs Documentation: KVM: Document KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS for VGICv5 Documentation: KVM: Add KVM_DEV_ARM_VGIC_GRP_IRS_REGS to VGICv5 docs Documentation: KVM: Add docs for KVM_DEV_ARM_VGIC_GRP_IST Documentation: KVM: Add the VGICv5 IRS save/restore sequences KVM: selftests: Add VGICv5 IRS address attribute tests KVM: selftests: Add VGICv5 NR_IRQS attribute tests KVM: selftests: Add VGICv5 IRS_REGS attribute tests KVM: selftests: Add VGICv5 IST attribute tests KVM: selftests: Add VGICv5 USERSPACE_PPIS tests KVM: selftests: Add VGICv5 CPU sysreg attribute tests KVM: selftests: Add VGICv5 SPI injection tests KVM: selftests: Add VGICv5 LPI delivery tests KVM: selftests: Add VGICv5 IST save/restore coverage KVM: selftests: Add VGICv5 sparse vCPU IDs test Documentation/virt/kvm/api.rst | 3 +- .../virt/kvm/devices/arm-vgic-v5.rst | 271 ++- arch/arm64/include/asm/kvm_asm.h | 3 + arch/arm64/include/asm/kvm_host.h | 1 + arch/arm64/include/asm/kvm_hyp.h | 3 + arch/arm64/include/asm/sysreg.h | 13 +- arch/arm64/include/uapi/asm/kvm.h | 15 + arch/arm64/kvm/Makefile | 3 +- arch/arm64/kvm/arm.c | 10 +- arch/arm64/kvm/hyp/nvhe/hyp-main.c | 35 + arch/arm64/kvm/hyp/vgic-v5-sr.c | 45 + arch/arm64/kvm/sys_regs.c | 6 +- arch/arm64/kvm/vgic-sys-reg-v5.c | 519 +++++ arch/arm64/kvm/vgic/vgic-init.c | 154 +- arch/arm64/kvm/vgic/vgic-irqfd.c | 18 +- arch/arm64/kvm/vgic/vgic-irs-v5.c | 1217 +++++++++++ arch/arm64/kvm/vgic/vgic-kvm-device.c | 270 ++- arch/arm64/kvm/vgic/vgic-mmio.c | 6 + arch/arm64/kvm/vgic/vgic-mmio.h | 2 + arch/arm64/kvm/vgic/vgic-v5-tables.c | 1875 ++++++++++++++++ arch/arm64/kvm/vgic/vgic-v5-tables.h | 140 ++ arch/arm64/kvm/vgic/vgic-v5.c | 1154 +++++++++- arch/arm64/kvm/vgic/vgic.c | 39 +- arch/arm64/kvm/vgic/vgic.h | 21 + arch/arm64/tools/sysreg | 4 +- drivers/irqchip/irq-gic-v5-irs.c | 19 +- drivers/irqchip/irq-gic-v5.c | 111 +- include/kvm/arm_vgic.h | 213 +- include/linux/irqchip/arm-gic-v5.h | 256 ++- include/linux/irqchip/arm-vgic-info.h | 5 + tools/arch/arm64/include/uapi/asm/kvm.h | 15 + tools/testing/selftests/kvm/arm64/vgic_v5.c | 1935 ++++++++++++++++- .../selftests/kvm/include/arm64/gic_v5.h | 105 + 33 files changed, 8280 insertions(+), 206 deletions(-) create mode 100644 arch/arm64/kvm/vgic-sys-reg-v5.c create mode 100644 arch/arm64/kvm/vgic/vgic-irs-v5.c create mode 100644 arch/arm64/kvm/vgic/vgic-v5-tables.c create mode 100644 arch/arm64/kvm/vgic/vgic-v5-tables.h --=20 2.34.1=