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Peter Anvin" , "Peter Zijlstra (Intel)" , Borislav Petkov , Dave Hansen , Ingo Molnar , "Mathieu Desnoyers" , Paolo Bonzini , Sairaj Kodilkar , "Sean Christopherson" , Thomas Gleixner , "Uros Bizjak" , , , CC: , Subject: [PATCH v4 1/2] x86/uaccess: Extend CMPXCHG user helpers to 128-bit operands Date: Tue, 8 Sep 2026 13:17:38 +0530 Message-ID: <20260908074739.10748-2-sarunkod@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260908074739.10748-1-sarunkod@amd.com> References: <20260908074739.10748-1-sarunkod@amd.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE30:EE_|IA1PR12MB7565:EE_ X-MS-Office365-Filtering-Correlation-Id: 1f44e31a-48ed-4d35-f204-08df0d7d8da8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|1800799024|7416014|376014|82310400026|23010399003|921020|3023799007|10067099003|18002099003|11063799006|56012099006|22082099003; X-Microsoft-Antispam-Message-Info: CQwgG9Z5VCovOTLrLOcUdJaT9A0BAuClSZM/F0vvRYNU/peSODXhB5yIKm2wnZS/tR4/7RTUPW0V4WNdutSGvgxPlZLYWGCSTZgZ8iPFBOtHBqrj8Au+tc+Z8zMMyb0/BjVYbfz7Sx/H08EUgUWGceUDYquxbF2t+NYkZnXYYNuIa3Td47D15RQDDCAqg2mGwm3YrrzFBmde5s836PbpyYCH34/CJiKBZlJGfEpS+UqE1GVPCbcrehPwyPqzVhap794oAYYuVaDuLBt1UWES4MSXL4mWIX45hnUbZaSFH+j2KXhrTYZFmavw42NHhiUoViIlGHLMrgilpy2P0CQQa55wSQAHNj5JBRjcjv1HPpOpOx7QsW+vA+haufe8+j0+raCiE0yswXgXle5rtNWS7raJgb+roDe9vQyxSgOIsUPING3w/3wiUMWpde2Ju0FbCYEMhCuUlAZc5i72FDZkiIiQvD4JnMpMPJGwjCbojAxM0aOWCvtb7+I5Szqq+FOAkRQ9u5aUspGRUu77gwI4YnSXi5VA7uHD00AwhPqDf3Pq+KZighV38/09kl2c9pxACtRYgW07eAWNIwOVe41CofhkhTZN/A16rQmDxN4Uxp2IzMt9cqlalyGGJU/aA4AGGc0r6XoTnkR4Qv2Efxdat02XbV16fXPVHR1Xx8ZZ4RFHEPlCQLTOuJee4F4FL60iih+FaCFdSVAN8XqB7XNbqXwDQDvxc3N3iZLSYPo509dP0hkF+65ouFMC3tLIM3A+ X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700016)(1800799024)(7416014)(376014)(82310400026)(23010399003)(921020)(3023799007)(10067099003)(18002099003)(11063799006)(56012099006)(22082099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: x/jxf11XZ3ieiIDasTe0dleONMePJb/TkwUi7aEhMs0nC33uaWe9T6H4EhCO/An+ayW0VTQ64Jvmsu9uS5RYSc2zw2ylgaKE3MUm1XBXzd/GJaQbzikPkXKa6kuHORy8drH5Jl/U/xJBrsGlZTLrUWeEZ+DiQk+i3adJ5BxZ7RBSOWhRLHqfqIIrqKl4JErF9APvXGseXxdQg+jq8ufgI+H24W++f+zUodp+AQZRIYHK5jvj4jehCQzkmee8Xq0vtWm32ZQoPdPkwBX36flpV2UppCElHp3lkXGayQXo4+gRD+R2onpkVfOkDKaWYaxFnJk6e8VwGGebwy0G3qECKSJGtcA9EaTv1RjTt+TZidDA2GjaxNTZCHy/Loi7V5af4MSN92YPQZUWWs+SkZnSss6NVxgGbXOi510efSx7wou9mPkpOA2kzfb5SyIRwIam X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Sep 2026 07:48:20.7745 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1f44e31a-48ed-4d35-f204-08df0d7d8da8 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE30.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB7565 Extend the existing user CMPXCHG helpers to support 16-byte operands on x86-64, using LOCK_PREFIX "cmpxchg16b". This mirrors the existing __try_cmpxchg64_user_asm() / cmpxchg8b path provided for 32-bit kernels, where KVM needs an atomic compare-exchange wider than the generic cmpxchg helper can provide. On 32-bit kernels, stub the helper to generate build failure because cmpxchg16b requires 64-bit GPRs and is not available. KVM uses this to atomically emulate guest cmpxchg16b on guest RAM mapped via userspace addresses. Signed-off-by: Sairaj Kodilkar --- arch/x86/include/asm/uaccess.h | 64 +++++++++++++++++++++++++++++++++- 1 file changed, 63 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/uaccess.h b/arch/x86/include/asm/uaccess.h index 3a0dd3c2b233..6e10a8a3ba4d 100644 --- a/arch/x86/include/asm/uaccess.h +++ b/arch/x86/include/asm/uaccess.h @@ -407,6 +407,27 @@ do { \ if (unlikely(!success)) \ *_old = __old; \ likely(success); }) +#else // !CONFIG_X86_32 +#define __try_cmpxchg128_user_asm(_ptr, _pold, _new, label) ({ \ + bool success; \ + __typeof__(_ptr) _old = (__typeof__(_ptr))(_pold); \ + u64 __old_low = (u64)*_old; \ + u64 __old_high = (u64)(*_old >> 64); \ + __typeof__(*(_ptr)) __new = (_new); \ + asm_goto_output("\n" \ + "1: " LOCK_PREFIX "cmpxchg16b %[ptr]\n" \ + _ASM_EXTABLE_UA(1b, %l[label]) \ + : "=@ccz" (success), \ + "+a" (__old_low), \ + "+d" (__old_high), \ + [ptr] "+m" (*_ptr) \ + : "b" ((u64)__new), \ + "c" ((u64)((u128)__new >> 64)) \ + : "memory" \ + : label); \ + if (unlikely(!success)) \ + *_old = ((u128)__old_high << 64) | __old_low; \ + likely(success); }) #endif // CONFIG_X86_32 #else // !CONFIG_CC_HAS_ASM_GOTO_TIED_OUTPUT #define __try_cmpxchg_user_asm(itype, ltype, _ptr, _pold, _new, label) ({ \ @@ -463,6 +484,32 @@ do { \ if (unlikely(!__result)) \ *_old = __old; \ likely(__result); }) +#else //!CONFIG_X86_32 +#define __try_cmpxchg128_user_asm(_ptr, _pold, _new, label) ({ \ + int __result; \ + __typeof__(_ptr) _old = (__typeof__(_ptr))(_pold); \ + u64 __old_low = (u64)*_old; \ + u64 __old_high = (u64)(*_old >> 64); \ + __typeof__(*(_ptr)) __new = (_new); \ + asm volatile("\n" \ + "1: " LOCK_PREFIX "cmpxchg16b %[ptr]\n" \ + "mov $0, %[result]\n\t" \ + "setz %b[result]\n" \ + "2:\n" \ + _ASM_EXTABLE_TYPE_REG(1b, 2b, EX_TYPE_EFAULT_REG, \ + %[result]) \ + : [result] "=q" (__result), \ + "+a" (__old_low), \ + "+d" (__old_high), \ + [ptr] "+m" (*_ptr) \ + : "b" ((u64)__new), \ + "c" ((u64)((u128)__new >> 64)) \ + : "memory", "cc"); \ + if (unlikely(__result < 0)) \ + goto label; \ + if (unlikely(!__result)) \ + *_old = ((u128)__old_high << 64) | __old_low; \ + likely(__result); }) #endif // CONFIG_X86_32 #endif // CONFIG_CC_HAS_ASM_GOTO_TIED_OUTPUT @@ -551,11 +598,18 @@ do { \ extern void __try_cmpxchg_user_wrong_size(void); -#ifndef CONFIG_X86_32 +#if defined(CONFIG_X86_32) || !defined(X86_FEATURE_CX16) +/* + * Always fail on 32 bit arch or 64 arch without 128 bit cmpxchg support + */ +#define __try_cmpxchg128_user_asm(_ptr, _pold, _new, label) ({ BUILD_BUG_ON(1); 0; }) +#else #define __try_cmpxchg64_user_asm(_ptr, _oldp, _nval, _label) \ __try_cmpxchg_user_asm("q", "r", (_ptr), (_oldp), (_nval), _label) + #endif + /* * Force the pointer to u to match the size expected by the asm helper. * clang/LLVM compiles all cases and only discards the unused paths after @@ -580,6 +634,14 @@ extern void __try_cmpxchg_user_wrong_size(void); case 8: __ret = __try_cmpxchg64_user_asm((__force u64 *)(_ptr), (_oldp),\ (_nval), _label); \ break; \ + case 16: \ + if (boot_cpu_has(X86_FEATURE_CX16)) \ + __ret = __try_cmpxchg128_user_asm( \ + (__force u128 *)(_ptr), \ + (_oldp), (_nval), _label); \ + else \ + __ret = 0; \ + break; \ default: __try_cmpxchg_user_wrong_size(); \ } \ __ret; }) -- 2.34.1