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Thu, 24 Sep 2026 10:29:37 -0700 (PDT) Date: Thu, 24 Sep 2026 17:29:11 +0000 In-Reply-To: <20260924172928.2110956-1-coltonlewis@google.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20260924172928.2110956-1-coltonlewis@google.com> X-Mailer: git-send-email 2.56.0.rc1.315.gc6ed9934b7-goog Message-ID: <20260924172928.2110956-6-coltonlewis@google.com> Subject: [PATCH v9 05/22] perf: arm_pmuv3: Move counter allocation mask to per-CPU struct pmu_hw_events From: Colton Lewis To: kvm@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org Cc: Marc Zyngier , Oliver Upton , Oliver Upton , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Fuad Tabba , Catalin Marinas , Will Deacon , Mark Rutland , Paolo Bonzini , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , James Clark , Robin Murphy , Zide Chen , Alexandru Elisei , Ganapatrao Kulkarni , Mingwei Zhang , Jonathan Corbet , Russell King , Shuah Khan , linux-perf-users@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, Colton Lewis Content-Type: text/plain; charset="UTF-8" In preparation for dynamic per-CPU PMU counter reservations when running KVM guests with a partitioned PMU, move the counter allocation mask from the global struct arm_pmu to per-CPU struct pmu_hw_events. Initialize cpuc->cntr_mask from the static cpu_pmu->cntr_mask during PMU probe and CPU hotplug startup, and update event counter allocation helpers (armv8pmu_get_single_idx(), armv8pmu_get_chain_idx(), and armv8pmu_get_event_idx()) to query the per-CPU mask. Signed-off-by: Colton Lewis --- drivers/perf/arm_pmu.c | 7 ++++++- drivers/perf/arm_pmuv3.c | 18 +++++++++++++----- include/linux/perf/arm_pmu.h | 1 + 3 files changed, 20 insertions(+), 6 deletions(-) diff --git a/drivers/perf/arm_pmu.c b/drivers/perf/arm_pmu.c index 1150695653892..344adcd3521d0 100644 --- a/drivers/perf/arm_pmu.c +++ b/drivers/perf/arm_pmu.c @@ -408,9 +408,11 @@ validate_group(struct perf_event *event) /* * Initialise the fake PMU. We only need to populate the - * used_mask for the purposes of validation. + * used_mask and cntr_mask for the purposes of validation. */ memset(&fake_pmu.used_mask, 0, sizeof(fake_pmu.used_mask)); + bitmap_copy(fake_pmu.cntr_mask, to_arm_pmu(event->pmu)->cntr_mask, + ARMPMU_MAX_HWEVENTS); if (!validate_event(event->pmu, &fake_pmu, leader)) return -EINVAL; @@ -717,6 +719,7 @@ bool arm_pmu_irq_is_nmi(void) static int arm_perf_starting_cpu(unsigned int cpu, struct hlist_node *node) { struct arm_pmu *pmu = hlist_entry_safe(node, struct arm_pmu, node); + struct pmu_hw_events *cpuc = per_cpu_ptr(pmu->hw_events, cpu); int irq; if (!cpumask_test_cpu(cpu, &pmu->supported_cpus)) @@ -724,6 +727,8 @@ static int arm_perf_starting_cpu(unsigned int cpu, struct hlist_node *node) if (pmu->reset) pmu->reset(pmu); + bitmap_copy(cpuc->cntr_mask, pmu->cntr_mask, ARMPMU_MAX_HWEVENTS); + irq = armpmu_get_cpu_irq(pmu, cpu); if (irq) per_cpu(cpu_irq_ops, cpu)->enable_pmuirq(irq); diff --git a/drivers/perf/arm_pmuv3.c b/drivers/perf/arm_pmuv3.c index 4a6c1f3bcea1f..49289e5993dd7 100644 --- a/drivers/perf/arm_pmuv3.c +++ b/drivers/perf/arm_pmuv3.c @@ -813,7 +813,7 @@ static void armv8pmu_enable_user_access(struct arm_pmu *cpu_pmu) write_pmuacr(mask); } else { /* Clear any unused counters to avoid leaking their contents */ - for_each_andnot_bit(i, cpu_pmu->cntr_mask, cpuc->used_mask, + for_each_andnot_bit(i, cpuc->cntr_mask, cpuc->used_mask, ARMPMU_MAX_HWEVENTS) { if (i == ARMV8_PMU_CYCLE_IDX) write_pmccntr(0); @@ -917,7 +917,7 @@ static irqreturn_t armv8pmu_handle_irq(struct arm_pmu *cpu_pmu) * to prevent skews in group events. */ armv8pmu_stop(cpu_pmu); - for_each_set_bit(idx, cpu_pmu->cntr_mask, ARMPMU_MAX_HWEVENTS) { + for_each_set_bit(idx, cpuc->cntr_mask, ARMPMU_MAX_HWEVENTS) { struct perf_event *event = cpuc->events[idx]; struct hw_perf_event *hwc; @@ -958,7 +958,7 @@ static int armv8pmu_get_single_idx(struct pmu_hw_events *cpuc, { int idx; - for_each_set_bit(idx, cpu_pmu->cntr_mask, ARMV8_PMU_MAX_GENERAL_COUNTERS) { + for_each_set_bit(idx, cpuc->cntr_mask, ARMV8_PMU_MAX_GENERAL_COUNTERS) { if (!test_and_set_bit(idx, cpuc->used_mask)) return idx; } @@ -974,7 +974,7 @@ static int armv8pmu_get_chain_idx(struct pmu_hw_events *cpuc, * Chaining requires two consecutive event counters, where * the lower idx must be even. */ - for_each_set_bit(idx, cpu_pmu->cntr_mask, ARMV8_PMU_MAX_GENERAL_COUNTERS) { + for_each_set_bit(idx, cpuc->cntr_mask, ARMV8_PMU_MAX_GENERAL_COUNTERS) { if (!(idx & 0x1)) continue; if (!test_and_set_bit(idx, cpuc->used_mask)) { @@ -1042,7 +1042,7 @@ static int armv8pmu_get_event_idx(struct pmu_hw_events *cpuc, */ if ((evtype == ARMV8_PMUV3_PERFCTR_INST_RETIRED) && !armv8pmu_event_get_threshold(&event->attr) && - test_bit(ARMV8_PMU_INSTR_IDX, cpu_pmu->cntr_mask) && + test_bit(ARMV8_PMU_INSTR_IDX, cpuc->cntr_mask) && !armv8pmu_event_want_user_access(event)) { if (!test_and_set_bit(ARMV8_PMU_INSTR_IDX, cpuc->used_mask)) return ARMV8_PMU_INSTR_IDX; @@ -1426,6 +1426,7 @@ static int armv8pmu_probe_pmu(struct arm_pmu *cpu_pmu) .present = false, }; int ret; + int cpu; ret = smp_call_function_any(&cpu_pmu->supported_cpus, __armv8pmu_probe_pmu, @@ -1441,6 +1442,13 @@ static int armv8pmu_probe_pmu(struct arm_pmu *cpu_pmu) if (ret) return ret; } + + for_each_possible_cpu(cpu) { + struct pmu_hw_events *cpuc = per_cpu_ptr(cpu_pmu->hw_events, cpu); + + bitmap_copy(cpuc->cntr_mask, cpu_pmu->cntr_mask, ARMPMU_MAX_HWEVENTS); + } + return 0; } diff --git a/include/linux/perf/arm_pmu.h b/include/linux/perf/arm_pmu.h index 02d2c7f45b527..be1e345e99a77 100644 --- a/include/linux/perf/arm_pmu.h +++ b/include/linux/perf/arm_pmu.h @@ -62,6 +62,7 @@ struct pmu_hw_events { * an event. A 0 means that the counter can be used. */ DECLARE_BITMAP(used_mask, ARMPMU_MAX_HWEVENTS); + DECLARE_BITMAP(cntr_mask, ARMPMU_MAX_HWEVENTS); /* * When using percpu IRQs, we need a percpu dev_id. Place it here as we -- 2.56.0.rc1.310.g51773c2048-goog