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Thu, 24 Sep 2026 10:29:38 -0700 (PDT) Date: Thu, 24 Sep 2026 17:29:12 +0000 In-Reply-To: <20260924172928.2110956-1-coltonlewis@google.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20260924172928.2110956-1-coltonlewis@google.com> X-Mailer: git-send-email 2.56.0.rc1.315.gc6ed9934b7-goog Message-ID: <20260924172928.2110956-7-coltonlewis@google.com> Subject: [PATCH v9 06/22] perf: arm_pmuv3: Check cntr_mask before using pmccntr From: Colton Lewis To: kvm@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org Cc: Marc Zyngier , Oliver Upton , Oliver Upton , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Fuad Tabba , Catalin Marinas , Will Deacon , Mark Rutland , Paolo Bonzini , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , James Clark , Robin Murphy , Zide Chen , Alexandru Elisei , Ganapatrao Kulkarni , Mingwei Zhang , Jonathan Corbet , Russell King , Shuah Khan , linux-perf-users@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, Colton Lewis Content-Type: text/plain; charset="UTF-8" When the PMU is partitioned, PMCCNTR_EL0 is reserved for the guest and removed from cpuc->cntr_mask. Move the PMCCNTR_EL0 availability checks (cpuc->cntr_mask and cpuc->used_mask) into armv8pmu_can_use_pmccntr() and un-nest the 64-bit user-access fallback check in armv8pmu_get_event_idx() so host CPU_CYCLES events fall back to general-purpose event counters when PMCCNTR_EL0 is unavailable. Signed-off-by: Colton Lewis --- drivers/perf/arm_pmuv3.c | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/drivers/perf/arm_pmuv3.c b/drivers/perf/arm_pmuv3.c index 49289e5993dd7..c15a34684137a 100644 --- a/drivers/perf/arm_pmuv3.c +++ b/drivers/perf/arm_pmuv3.c @@ -1015,6 +1015,10 @@ static bool armv8pmu_can_use_pmccntr(struct pmu_hw_events *cpuc, if (cpu_pmu->avoid_pmccntr) return false; + if (!test_bit(ARMV8_PMU_CYCLE_IDX, cpuc->cntr_mask) || + test_bit(ARMV8_PMU_CYCLE_IDX, cpuc->used_mask)) + return false; + return true; } @@ -1027,14 +1031,15 @@ static int armv8pmu_get_event_idx(struct pmu_hw_events *cpuc, /* Always prefer to place a cycle counter into the cycle counter. */ if (armv8pmu_can_use_pmccntr(cpuc, event)) { - if (!test_and_set_bit(ARMV8_PMU_CYCLE_IDX, cpuc->used_mask)) - return ARMV8_PMU_CYCLE_IDX; - else if (armv8pmu_event_is_64bit(event) && - armv8pmu_event_want_user_access(event) && - !armv8pmu_has_long_event(cpu_pmu)) - return -EAGAIN; + set_bit(ARMV8_PMU_CYCLE_IDX, cpuc->used_mask); + return ARMV8_PMU_CYCLE_IDX; } + if (armv8pmu_event_is_64bit(event) && + armv8pmu_event_want_user_access(event) && + !armv8pmu_has_long_event(cpu_pmu)) + return -EAGAIN; + /* * Always prefer to place a instruction counter into the instruction counter, * but don't expose the instruction counter to userspace access as userspace -- 2.56.0.rc1.310.g51773c2048-goog