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[86.49.245.11]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-6aae5dc0cddsm4296359a12.14.2026.09.28.07.32.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Sep 2026 07:32:18 -0700 (PDT) From: Andrew Jones To: iommu@lists.linux.dev, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: tomasz.jeznach@linux.dev, jgg@ziepe.ca, jgg@nvidia.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, tglx@kernel.org, anup@brainfault.org, atish.patra@linux.dev, fangyu.yu@linux.alibaba.com, zhangzhanpeng.jasper@bytedance.com, zong.li@sifive.com Subject: [RFC PATCH v3 12/14] iommu/riscv: Prepare interrupt remapping for IRQ bypass Date: Mon, 28 Sep 2026 16:31:11 +0200 Message-ID: <20260928143113.49838-13-andrew.jones@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260928143113.49838-1-andrew.jones@oss.qualcomm.com> References: <20260928143113.49838-1-andrew.jones@oss.qualcomm.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-GUID: GN06vIwAfE5TmRqgJYglba1-IVjQfoMT X-Proofpoint-ORIG-GUID: GN06vIwAfE5TmRqgJYglba1-IVjQfoMT X-Proofpoint-Spam-Info: AW1haW4tMjYwOTI4MDA1OCBTYWx0ZWRfX8+s3O59xYjcg uzD3414YI/qRqRusTUe0BaOnvCinQ6kgmPhfLUYBOAQvz9+K9XXodRQSkPtqqJlAwX6kVtKw0Xa +9vznDWMDAf1fXZuTttgByqR8svcKGc= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTI4MDA1OCBTYWx0ZWRfXxF5TQNl2VgSf EazDYoS4RoAS4vcWtbOT77C0YGt2kijDH6imQF9TUMsLwlEuW1W11LGBxRgr937MZJvGrK3tjhr Pj7673p+GhOIST5gnWxSpfoA9cgSCYMhW6HHZmlVzkubPeooap6HP6lnx3o4/DzOFs4R0IkztIq vEGOy+CzCGVeYJeOoKsQGSBnYPWuSGbqh0L/VeiHtJ+WSn6zF6E2nPNH9t1VACEn+JX4BaXbCmR po+plBfrXi4WKWK7wVSc+R5Vyvt9HY6iUWYRZ1q21bLXl8oopRaMYXYYVAaq3Z9nFd3rooijVNZ pt7pJQksrTR60aPl+BUIu8X3ibkpL6LBt2gjXjPut1/HPonbZGJv7fXIdRFuhoHxQ2JCve8I8v0 umh8z7m1p56WCoqHqnQgnZx7v2NzqSigCed+FjDh1OpAe8FlEjLJ/60y4nG9AH3zjrKTFrwgCi1 Y5Q+5Xm7G7TXe/0iHhw== X-Authority-Analysis: v=2.4 cv=QZfzLcbv c=1 sm=1 tr=0 ts=6aba7bee cx=c_pps a=yymyAM/LQ7lj/HqAiIiKTw==:117 a=4CXLxsOAgPM/krjtHEZQyA==:17 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=EUspDBNiAAAA:8 a=E4clnSanGcVZL-NzkHIA:9 a=efpaJB4zofY2dbm2aIRb:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-28_03,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 bulkscore=0 priorityscore=1501 phishscore=0 impostorscore=0 suspectscore=0 clxscore=1015 adultscore=0 lowpriorityscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609280058 IRQ bypass changes the meaning of an interrupt from host delivery to delivery through the guest's MSI table. The transition therefore has to follow the device's current IOMMU domain and must not race with a domain replacement. Wire the interrupt-remapping irqdomain into irq_set_vcpu_affinity() and serialize the callback with MSI-table publication and attachment. Since one table is shared by every device in the domain, also require all forwarded interrupts to agree on its owner and address layout. Leave the hardware operations as stubs so the locking and state-machine requirements are established before MSI PTE programming is added. Signed-off-by: Andrew Jones --- drivers/iommu/riscv/iommu-ir.c | 140 ++++++++++++++++++++++++++++++++- drivers/iommu/riscv/iommu.h | 1 + 2 files changed, 140 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/riscv/iommu-ir.c b/drivers/iommu/riscv/iommu-ir.c index c5603cb9f258..22da76987c7c 100644 --- a/drivers/iommu/riscv/iommu-ir.c +++ b/drivers/iommu/riscv/iommu-ir.c @@ -11,12 +11,150 @@ #include "iommu.h" +static int riscv_iommu_ir_irq_set_affinity(struct irq_data *data, + const struct cpumask *mask, bool force) +{ + if (irqd_is_forwarded_to_vcpu(data)) + return -EINVAL; + + return irq_chip_set_affinity_parent(data, mask, force); +} + +static int riscv_iommu_ir_activate(struct riscv_iommu_msi_table *msi_table, + struct riscv_iommu_ir_vcpu_info *vcpu_info) +{ + return -EOPNOTSUPP; +} + +static int riscv_iommu_ir_deactivate(struct riscv_iommu_msi_table *msi_table) +{ + return -EOPNOTSUPP; +} + +static int riscv_iommu_ir_update_target(struct riscv_iommu_msi_table *msi_table, + struct riscv_iommu_ir_vcpu_info *vcpu_info) +{ + return -EOPNOTSUPP; +} + +static int riscv_iommu_ir_irq_set_vcpu_affinity_locked(struct irq_data *data, + struct riscv_iommu_info *info, + struct riscv_iommu_ir_vcpu_info *vcpu_info, + struct riscv_iommu_msi_table *msi_table) +{ + int ret; + + if (!vcpu_info) { + if (WARN_ON_ONCE(!msi_table->nr_forwarded_irqs || !info->nr_forwarded_irqs)) + return -EINVAL; + + if (msi_table->nr_forwarded_irqs == 1) { + ret = riscv_iommu_ir_deactivate(msi_table); + if (ret) + return ret; + } + + msi_table->nr_forwarded_irqs--; + info->nr_forwarded_irqs--; + irqd_clr_forwarded_to_vcpu(data); + + if (!msi_table->nr_forwarded_irqs) { + msi_table->owner = NULL; + msi_table->msi_addr_mask = 0; + msi_table->msi_addr_pattern = 0; + } + + return 0; + } + + if (!msi_table->nr_forwarded_irqs) { + if (vcpu_info->cmd == RISCV_IOMMU_IR_UPDATE_TARGET || + irqd_is_forwarded_to_vcpu(data)) + return -EINVAL; + + ret = riscv_iommu_ir_activate(msi_table, vcpu_info); + if (ret) + return ret; + + msi_table->nr_forwarded_irqs++; + info->nr_forwarded_irqs++; + irqd_set_forwarded_to_vcpu(data); + + return 0; + } + + if (msi_table->owner != vcpu_info->owner || + msi_table->msi_addr_mask != vcpu_info->msi_addr_mask || + msi_table->msi_addr_pattern != vcpu_info->msi_addr_pattern) + return -EOPNOTSUPP; + + if (vcpu_info->cmd == RISCV_IOMMU_IR_FORWARD) { + if (!irqd_is_forwarded_to_vcpu(data)) { + msi_table->nr_forwarded_irqs++; + info->nr_forwarded_irqs++; + irqd_set_forwarded_to_vcpu(data); + } + return 0; + } + + return riscv_iommu_ir_update_target(msi_table, vcpu_info); +} + +static int riscv_iommu_ir_irq_set_vcpu_affinity(struct irq_data *data, void *arg) +{ + struct riscv_iommu_ir_vcpu_info *vcpu_info = arg; + struct riscv_iommu_msi_table *msi_table; + struct riscv_iommu_info *info; + struct msi_desc *desc; + struct device *dev; + int ret; + + if (!vcpu_info && !irqd_is_forwarded_to_vcpu(data)) + return 0; + + if (vcpu_info && vcpu_info->cmd != RISCV_IOMMU_IR_FORWARD && + (vcpu_info->cmd != RISCV_IOMMU_IR_UPDATE_TARGET || !irqd_is_forwarded_to_vcpu(data))) + return -EINVAL; + + desc = irq_data_get_msi_desc(data); + if (WARN_ON_ONCE(!desc)) + return -EINVAL; + + dev = msi_desc_to_dev(desc); + info = dev_iommu_priv_get(dev); + if (WARN_ON_ONCE(!info)) + return -EINVAL; + + scoped_guard(rcu) { + /* + * RCU keeps the table alive, but the device may switch domains before + * the table is locked. Recheck the association under the lock. + */ + for (;;) { + msi_table = riscv_iommu_msi_table_rcu(info); + if (!msi_table || !msi_table->root) + return -EOPNOTSUPP; + + raw_spin_lock(&msi_table->lock); + if (msi_table == riscv_iommu_msi_table_rcu(info)) + break; + raw_spin_unlock(&msi_table->lock); + } + } + + ret = riscv_iommu_ir_irq_set_vcpu_affinity_locked(data, info, vcpu_info, msi_table); + raw_spin_unlock(&msi_table->lock); + + return ret; +} + static struct irq_chip riscv_iommu_ir_irq_chip = { .name = "IOMMU-IR", .irq_ack = irq_chip_ack_parent, .irq_mask = irq_chip_mask_parent, .irq_unmask = irq_chip_unmask_parent, - .irq_set_affinity = irq_chip_set_affinity_parent, + .irq_set_affinity = riscv_iommu_ir_irq_set_affinity, + .irq_set_vcpu_affinity = riscv_iommu_ir_irq_set_vcpu_affinity, }; static int riscv_iommu_ir_irq_domain_alloc_irqs(struct irq_domain *irqdomain, diff --git a/drivers/iommu/riscv/iommu.h b/drivers/iommu/riscv/iommu.h index ed973979d795..a42f0b6a88d4 100644 --- a/drivers/iommu/riscv/iommu.h +++ b/drivers/iommu/riscv/iommu.h @@ -82,6 +82,7 @@ struct riscv_iommu_msi_table { struct riscv_iommu_msipte *root; u64 msi_addr_mask; u64 msi_addr_pattern; + const void *owner; }; /* Private IOMMU data for managed devices, dev_iommu_priv_* */ -- 2.43.0