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[86.49.245.11]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-6aae5dc097csm4205378a12.12.2026.09.28.07.31.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Sep 2026 07:31:36 -0700 (PDT) From: Andrew Jones To: iommu@lists.linux.dev, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: tomasz.jeznach@linux.dev, jgg@ziepe.ca, jgg@nvidia.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, tglx@kernel.org, anup@brainfault.org, atish.patra@linux.dev, fangyu.yu@linux.alibaba.com, zhangzhanpeng.jasper@bytedance.com, zong.li@sifive.com Subject: [RFC PATCH v3 02/14] iommu/riscv: Prepare domain bonds for outer locking Date: Mon, 28 Sep 2026 16:31:01 +0200 Message-ID: <20260928143113.49838-3-andrew.jones@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260928143113.49838-1-andrew.jones@oss.qualcomm.com> References: <20260928143113.49838-1-andrew.jones@oss.qualcomm.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=Sq4Fe/O0 c=1 sm=1 tr=0 ts=6aba7a55 cx=c_pps a=DUEm7b3gzWu7BqY5nP7+9g==:117 a=4CXLxsOAgPM/krjtHEZQyA==:17 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=EUspDBNiAAAA:8 a=69OsnF3JIPtLgHPxktkA:9 a=-aSRE8QhW-JAV6biHavz:22 X-Proofpoint-GUID: wiE52XzPpFbyRMKK7CEKvpvymn-fvgZz X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTI4MDA1NyBTYWx0ZWRfX5cTKxBCab21q 0fWJMk/xMaHKfd0z9Dm/s6/KZQUGdTumgcrt0n0KsynsuVorLtSS5Qst+fuyF0f8dyo4anC1vbN hYE5OEHvGW0Xtn8m/LK3nk9yrISBX6qkWoMK3+70wZYdX/pPOWksV9G39zMojf1+ZTZW1cEnZDm iUFt0g4+hKtA8S8ZQWpzAmyKq/3E9poeqToo+7kZ2r8+wsXAQWpwix2WZx2QjtwAiR3/f5+0BkE sjo4FPX109Gl3l0iZn9RYqCg2rbiYFpCypY7C51UWgiOKoHFgOIjKg5aPTCxYyWr4z5UKyCKP+Z G2dZPnX9pXyhKrxqmV4NM3buzo/XOyWIeIWevmKM0Z0bHRUZ9p2Dy3sLyU1Ju/PkNRJwRqHXDaY yolfz+gCcurFVvZZdH/dp4xueLtal9R+ZJN9D2E6rVT47ULGfAq5Tueqkl8uY41CtYT4iIUGHuv WnzO79p6F7h9nU4sveA== X-Proofpoint-Spam-Info: AW1haW4tMjYwOTI4MDA1NyBTYWx0ZWRfX/xzSoe/JE5uw 30dK151UOv8TZH0Vnh3EGzhVwsYGIYkF0ZSNqq27Hg+Y8LHxcrtRVXb/PMzSDdmAOv6v2uvtEkW yKFQw3PZfcVcryC7KEsY7ljVYv6GMas= X-Proofpoint-ORIG-GUID: wiE52XzPpFbyRMKK7CEKvpvymn-fvgZz X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-28_03,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 clxscore=1015 priorityscore=1501 bulkscore=0 malwarescore=0 adultscore=0 phishscore=0 spamscore=0 lowpriorityscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609280057 IRQ bypass will serialize attachment under a raw spinlock. Bond updates retain their own lock, so make it raw for safe PREEMPT_RT nesting. MSI forwarding will acquire the MSI table lock under the hardirq-safe IRQ descriptor lock. Nesting the bond lock below the MSI table lock therefore requires IRQ protection even for domains without an MSI table, where attachment takes only the bond lock. Use irqsave/irqrestore in both bond helpers to avoid a HARDIRQ-safe to HARDIRQ-unsafe lock dependency. Also split allocation from list insertion so a future outer lock can be taken after the sleeping allocation. No functional change intended. Signed-off-by: Andrew Jones --- drivers/iommu/riscv/iommu.c | 34 ++++++++++++++++------------------ 1 file changed, 16 insertions(+), 18 deletions(-) diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c index 3bbb4d0d0a85..09ec8c3e4a72 100644 --- a/drivers/iommu/riscv/iommu.c +++ b/drivers/iommu/riscv/iommu.c @@ -858,7 +858,7 @@ struct riscv_iommu_domain { struct pt_iommu_riscv_64 riscvpt; }; struct list_head bonds; - spinlock_t lock; /* protect bonds list updates. */ + raw_spinlock_t lock; /* protect bonds list updates. */ struct mutex mutex; /* serialize domain state updates */ int pscid; int gscid; @@ -896,34 +896,27 @@ struct riscv_iommu_bond { struct device *dev; }; -static int riscv_iommu_bond_link(struct riscv_iommu_domain *domain, - struct device *dev) +static void riscv_iommu_bond_link(struct riscv_iommu_domain *domain, + struct riscv_iommu_bond *bond) { - struct riscv_iommu_device *iommu = dev_to_iommu(dev); - struct riscv_iommu_bond *bond; + struct riscv_iommu_device *iommu = dev_to_iommu(bond->dev); struct list_head *bonds; - - bond = kzalloc_obj(*bond); - if (!bond) - return -ENOMEM; - bond->dev = dev; + unsigned long flags; /* * List of devices attached to the domain is arranged based on * managed IOMMU device. */ - spin_lock(&domain->lock); + raw_spin_lock_irqsave(&domain->lock, flags); list_for_each(bonds, &domain->bonds) if (dev_to_iommu(list_entry(bonds, struct riscv_iommu_bond, list)->dev) == iommu) break; list_add_rcu(&bond->list, bonds); - spin_unlock(&domain->lock); + raw_spin_unlock_irqrestore(&domain->lock, flags); /* Synchronize with riscv_iommu_iotlb_inval() sequence. See comment below. */ smp_mb(); - - return 0; } static void riscv_iommu_bond_unlink(struct riscv_iommu_domain *domain, @@ -932,12 +925,13 @@ static void riscv_iommu_bond_unlink(struct riscv_iommu_domain *domain, struct riscv_iommu_device *iommu = dev_to_iommu(dev); struct riscv_iommu_bond *bond, *found = NULL; struct riscv_iommu_command cmd; + unsigned long flags; int count = 0; if (!domain) return; - spin_lock(&domain->lock); + raw_spin_lock_irqsave(&domain->lock, flags); list_for_each_entry(bond, &domain->bonds, list) { if (found && count) break; @@ -948,7 +942,7 @@ static void riscv_iommu_bond_unlink(struct riscv_iommu_domain *domain, } if (found) list_del_rcu(&found->list); - spin_unlock(&domain->lock); + raw_spin_unlock_irqrestore(&domain->lock, flags); kfree_rcu(found, rcu); /* @@ -1391,6 +1385,7 @@ static int riscv_iommu_attach_paging_domain(struct iommu_domain *iommu_domain, struct riscv_iommu_domain *domain = iommu_domain_to_riscv(iommu_domain); struct riscv_iommu_device *iommu = dev_to_iommu(dev); struct riscv_iommu_info *info = dev_iommu_priv_get(dev); + struct riscv_iommu_bond *bond; struct pt_iommu_riscv_64_hw_info pt_info; struct riscv_iommu_dc dc = {0}; int ret; @@ -1421,9 +1416,12 @@ static int riscv_iommu_attach_paging_domain(struct iommu_domain *iommu_domain, dc.ta = FIELD_PREP(RISCV_IOMMU_PC_TA_PSCID, domain->pscid) | RISCV_IOMMU_PC_TA_V; - if (riscv_iommu_bond_link(domain, dev)) + bond = kzalloc_obj(*bond); + if (!bond) return -ENOMEM; + bond->dev = dev; + riscv_iommu_bond_link(domain, bond); riscv_iommu_iodir_update(iommu, dev, &dc); riscv_iommu_bond_unlink(info->domain, dev); info->domain = domain; @@ -1475,7 +1473,7 @@ riscv_iommu_domain_alloc_paging_flags(struct device *dev, u32 flags, return ERR_PTR(-ENOMEM); INIT_LIST_HEAD_RCU(&domain->bonds); - spin_lock_init(&domain->lock); + raw_spin_lock_init(&domain->lock); mutex_init(&domain->mutex); iommu = dev_to_iommu(dev); cfg.common.hw_max_oasz_lg2 = 56; -- 2.43.0