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[86.49.245.11]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c2dbd110c3esm296984266b.63.2026.09.28.07.32.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Sep 2026 07:32:08 -0700 (PDT) From: Andrew Jones To: iommu@lists.linux.dev, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: tomasz.jeznach@linux.dev, jgg@ziepe.ca, jgg@nvidia.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, tglx@kernel.org, anup@brainfault.org, atish.patra@linux.dev, fangyu.yu@linux.alibaba.com, zhangzhanpeng.jasper@bytedance.com, zong.li@sifive.com Subject: [RFC PATCH v3 07/14] iommu/riscv: Prepare MSI table updates for interrupt remapping Date: Mon, 28 Sep 2026 16:31:06 +0200 Message-ID: <20260928143113.49838-8-andrew.jones@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260928143113.49838-1-andrew.jones@oss.qualcomm.com> References: <20260928143113.49838-1-andrew.jones@oss.qualcomm.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=Sq4Fe/O0 c=1 sm=1 tr=0 ts=6aba7a6b cx=c_pps a=P2rfLEam3zuxRRdjJWA2cw==:117 a=4CXLxsOAgPM/krjtHEZQyA==:17 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=EUspDBNiAAAA:8 a=tpFWYQdyHN71iLxetsoA:9 a=ODZdjJIeia2B_SHc_B0f:22 X-Proofpoint-GUID: Ysbm0td4pGpL0pWK6HtL7Z0fbWDfUmQw X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTI4MDA1NyBTYWx0ZWRfXxnp1C+v2bg3+ DNQyUQ3GuOPQlAhLp+5tyM+K6XWhYoa8oifl3aifdDQC4dI6sT6+DFKEYs2M6wmjjbn4pFN1q05 BrH/uUXGaRFMGU2WPLWCB2no4hFtfS7oj2zFtnYA2pKl5RRunllOVWWTjeXyg3yKDdFbkt1PZ2/ jhxAhd6Yz/W4buJzY3pGpZM0kVCKLfvDsFcyXGGjNMX6GkvYXU/ra6Bv9TJiU/CKoyUoC9et+BC bcXmSPKFL6BuwcvKpO+Lz6+1lb7fteZpbrI/vy2VjK3hDpp72MfD/xbhzvMcyyrSStEtDOclq70 Z6HgOYF7gqg0MWrl87h7rrBx9aZ1n9DI+S9EJeh5muzAHmt3p7DEb/lJ0CgUGZZti1vsqfS3Z9z pTsYIc204f2DIHdjd3Samm2EFy7DGYsHAhfUI8mci3bs8B1zkVi1HSDwT+Mn3OWLB9T7ug7/tnJ zOPlB2ZVH0AwTj6XZgQ== X-Proofpoint-Spam-Info: AW1haW4tMjYwOTI4MDA1NyBTYWx0ZWRfX6QasVa/Htm5O hP8ES1kHMkWb3B2iRDvxCT1eoyMtxR3XwddDxgf3sdk3X6+J4dScO4YofNfMwk+o5Sbwl3mUGOK 8/gBSSNGD/xCxCSlbxk83+X4mlj1wro= X-Proofpoint-ORIG-GUID: Ysbm0td4pGpL0pWK6HtL7Z0fbWDfUmQw X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-28_03,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 clxscore=1015 priorityscore=1501 bulkscore=0 malwarescore=0 adultscore=0 phishscore=0 spamscore=0 lowpriorityscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609280057 Guest interrupt-file mappings require interrupt-remapping code to install or remove the MSI page-table pointer and address extraction fields in every device context attached to a domain. Devices joining an active MSI domain also need their device contexts initialized, so check for an active MSI domain at attach time. Add helpers to publish those fields to bonded devices and to invalidate one or all MSI PTE translations. These helpers will be used by the IRQ bypass implementation. The per-device nr_forwarded_irqs counter is insufficient to detect active MSI tables for the domain, so we introduce another counter which is domain-wide. Like info->nr_forwarded_irqs, later patches which introduce interrupt remapping support will manage the newly introduced nr_forwarded_irqs counter. Signed-off-by: Andrew Jones --- drivers/iommu/riscv/iommu.c | 65 +++++++++++++++++++++++++++++++++++++ drivers/iommu/riscv/iommu.h | 5 +++ 2 files changed, 70 insertions(+) diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c index 86d5795a12dd..db4539fbcb95 100644 --- a/drivers/iommu/riscv/iommu.c +++ b/drivers/iommu/riscv/iommu.c @@ -1189,6 +1189,28 @@ static void riscv_iommu_iotlb_inval(struct riscv_iommu_domain *domain, rcu_read_unlock(); } +void riscv_iommu_msi_table_inval(struct riscv_iommu_msi_table *msi_table, unsigned long addr) +{ + struct iommu_iotlb_gather gather = { + .start = addr, + .end = addr + SZ_4K - 1, + .pt.leaf_levels_bitmap = 1, + }; + struct riscv_iommu_domain *domain; + + domain = container_of(msi_table, struct riscv_iommu_domain, msi_table); + riscv_iommu_iotlb_inval(domain, &gather); +} + +void riscv_iommu_msi_table_inval_all(struct riscv_iommu_msi_table *msi_table) +{ + struct iommu_iotlb_gather gather = { 0 }; + struct riscv_iommu_domain *domain; + + domain = container_of(msi_table, struct riscv_iommu_domain, msi_table); + riscv_iommu_iotlb_inval(domain, &gather); +} + #define RISCV_IOMMU_FSC_BARE 0 /* * This function sends IOTINVAL commands as required by the RISC-V @@ -1311,6 +1333,11 @@ static void riscv_iommu_iodir_update(struct device *dev, struct riscv_iommu_dc * WRITE_ONCE(dc->fsc, new_dc->fsc); WRITE_ONCE(dc->ta, new_dc->ta & RISCV_IOMMU_PC_TA_PSCID); WRITE_ONCE(dc->iohgatp, new_dc->iohgatp); + if (iommu->caps & RISCV_IOMMU_CAPABILITIES_MSI_FLAT) { + WRITE_ONCE(dc->msiptp, new_dc->msiptp); + WRITE_ONCE(dc->msi_addr_mask, new_dc->msi_addr_mask); + WRITE_ONCE(dc->msi_addr_pattern, new_dc->msi_addr_pattern); + } /* Update device context, write TC.V as the last step. */ dma_wmb(); WRITE_ONCE(dc->tc, tc); @@ -1329,6 +1356,40 @@ static void riscv_iommu_iodir_update(struct device *dev, struct riscv_iommu_dc * riscv_iommu_cmd_sync(iommu, RISCV_IOMMU_IOTINVAL_TIMEOUT); } +static void riscv_iommu_msi_table_set_dc(struct riscv_iommu_msi_table *msi_table, + struct riscv_iommu_dc *dc, bool activate) +{ + if (activate) { + dc->msiptp = virt_to_pfn(msi_table->root) | + FIELD_PREP(RISCV_IOMMU_DC_MSIPTP_MODE, + RISCV_IOMMU_DC_MSIPTP_MODE_FLAT); + dc->msi_addr_mask = msi_table->msi_addr_mask; + dc->msi_addr_pattern = msi_table->msi_addr_pattern; + } else { + dc->msiptp = 0; + dc->msi_addr_mask = 0; + dc->msi_addr_pattern = 0; + } +} + +void riscv_iommu_msi_table_update(struct riscv_iommu_msi_table *msi_table, bool activate) +{ + struct riscv_iommu_domain *domain; + struct riscv_iommu_bond *bond; + + /* The MSI table lock excludes bond updates for this domain. */ + lockdep_assert_held(&msi_table->lock); + + domain = container_of(msi_table, struct riscv_iommu_domain, msi_table); + + list_for_each_entry(bond, &domain->bonds, list) { + struct riscv_iommu_info *info = dev_iommu_priv_get(bond->dev); + + riscv_iommu_msi_table_set_dc(msi_table, &info->dc, activate); + riscv_iommu_iodir_update(bond->dev, &info->dc); + } +} + /* * IOVA page translation tree management. */ @@ -1514,6 +1575,10 @@ static int riscv_iommu_attach_paging_domain(struct iommu_domain *iommu_domain, kfree(bond); return -EBUSY; } + + if (domain->msi_table.nr_forwarded_irqs) + riscv_iommu_msi_table_set_dc(&domain->msi_table, &dc, true); + info->dc = dc; riscv_iommu_bond_link(domain, bond); riscv_iommu_iodir_update(dev, &info->dc); diff --git a/drivers/iommu/riscv/iommu.h b/drivers/iommu/riscv/iommu.h index 2876703a6698..deb57b6a6c4b 100644 --- a/drivers/iommu/riscv/iommu.h +++ b/drivers/iommu/riscv/iommu.h @@ -71,6 +71,7 @@ struct riscv_iommu_device { struct riscv_iommu_msi_table { /* Protects attachment, interrupt forwarding state, and MSI PTE updates. */ raw_spinlock_t lock; + unsigned int nr_forwarded_irqs; unsigned int nr_ptes; struct riscv_iommu_msipte *root; u64 msi_addr_mask; @@ -81,6 +82,10 @@ int riscv_iommu_init(struct riscv_iommu_device *iommu); void riscv_iommu_remove(struct riscv_iommu_device *iommu); void riscv_iommu_disable(struct riscv_iommu_device *iommu); +void riscv_iommu_msi_table_inval(struct riscv_iommu_msi_table *msi_table, unsigned long addr); +void riscv_iommu_msi_table_inval_all(struct riscv_iommu_msi_table *msi_table); +void riscv_iommu_msi_table_update(struct riscv_iommu_msi_table *msi_table, bool activate); + #define riscv_iommu_readl(iommu, addr) \ readl_relaxed((iommu)->reg + (addr)) -- 2.43.0