From: Sean Christopherson <seanjc@google.com>
To: Paolo Bonzini <pbonzini@redhat.com>
Cc: kvm@vger.kernel.org, Sandipan Das <sandipan.das@amd.com>,
Sean Christopherson <seanjc@google.com>
Subject: [kvm-unit-tests PATCH] x86/pmu: Treat all AMD CPUs as having instruction/branch overcount errata
Date: Wed, 30 Sep 2026 14:02:01 -0700 [thread overview]
Message-ID: <20260930210201.3482775-1-seanjc@google.com> (raw)
Apply the instructions and branches overcount errata to all AMD CPUs, which
count VMRUN as a retired branch instruction in guest context. I.e. any
asynchronous #VMEXITs during any measurement will result in an overcount.
Reported-by: Sandipan Das <sandipan.das@amd.com>
Signed-off-by: Sean Christopherson <seanjc@google.com>
---
lib/x86/pmu.c | 7 +++++++
x86/pmu.c | 7 +------
2 files changed, 8 insertions(+), 6 deletions(-)
diff --git a/lib/x86/pmu.c b/lib/x86/pmu.c
index 67f3b23e..3231ce2d 100644
--- a/lib/x86/pmu.c
+++ b/lib/x86/pmu.c
@@ -72,6 +72,13 @@ void pmu_init(void)
pmu.msr_global_status_clr = MSR_CORE_PERF_GLOBAL_OVF_CTRL;
}
} else {
+ /*
+ * All AMD CPUs overcount instructions and branches retired, as
+ * they count VMRUN as a branch instruction in guest context.
+ */
+ pmu.errata.instructions_retired_overcount = true;
+ pmu.errata.branches_retired_overcount = true;
+
if (this_cpu_has(X86_FEATURE_PERFCTR_CORE)) {
/* Performance Monitoring Version 2 Supported */
if (this_cpu_has(X86_FEATURE_AMD_PMU_V2)) {
diff --git a/x86/pmu.c b/x86/pmu.c
index b262ea59..35f8a818 100644
--- a/x86/pmu.c
+++ b/x86/pmu.c
@@ -222,13 +222,8 @@ static void adjust_events_range(struct pmu_event *gp_events,
* If HW supports GLOBAL_CTRL MSR, enabling and disabling PMCs are
* moved in __precise_loop(). Thus, instructions and branches events
* can be verified against a precise count instead of a rough range.
- *
- * Skip the precise checks on AMD, as AMD CPUs count VMRUN as a branch
- * instruction in guest context, which* leads to intermittent failures
- * as the counts will vary depending on how many asynchronous VM-Exits
- * occur while running the measured code, e.g. if the host takes IRQs.
*/
- if (pmu.is_intel && this_cpu_has_perf_global_ctrl()) {
+ if (this_cpu_has_perf_global_ctrl()) {
if (!pmu.errata.instructions_retired_overcount) {
gp_events[instruction_idx].min = LOOP_INSNS;
gp_events[instruction_idx].max = LOOP_INSNS;
base-commit: 5a221342a025948fa7d84f0c404748f6ba57f3ad
--
2.56.0.rc1.315.gc6ed9934b7-goog
next reply other threads:[~2026-09-30 21:02 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-30 21:02 Sean Christopherson [this message]
2026-10-01 7:48 ` [kvm-unit-tests PATCH] x86/pmu: Treat all AMD CPUs as having instruction/branch overcount errata Sandipan Das
2026-10-01 23:38 ` Sean Christopherson
2026-10-02 21:07 ` Sean Christopherson
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