Re: [PATCH v15 07/23] KVM: selftests: Add TDX boot code

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Medium] kvm: selftests: missing wrmsr to set EFER.LME in TDX boot code
- [Medium] kvm: selftests: incorrect register used for TDX vCPU index
--

commit 0050b7c1fa5f321a19fe7395b74ac22ea9e52f99
Author: Erdem Aktas <erdemaktas@google.com>

KVM: selftests: Add TDX boot code

This commit adds assembly code to boot a TDX test VM. It loads relevant boot
parameters from memory into registers before jumping to the guest code.

> diff --git a/tools/testing/selftests/kvm/lib/x86/tdx/td_boot.S b/tools/testing/selftests/kvm/lib/x86/tdx/td_boot.S
> new file mode 100644
> index 0000000000000..726ec51e040e8
> --- /dev/null
> +++ b/tools/testing/selftests/kvm/lib/x86/tdx/td_boot.S
> @@ -0,0 +1,65 @@

[ ... ]

> +	/*
> +	 * Find the address of struct td_per_vcpu_parameters for this
> +	 * vCPU based on esi (TDX spec: initialized with vCPU id). Put
> +	 * struct address into eax for indirect addressing.
> +	 */
> +	movl $SIZEOF_TD_PER_VCPU_PARAMETERS, %eax
> +	mul %esi

[Severity: Medium]
Is it correct to read the vCPU index from %esi in td_boot here?

According to the TDX architecture specification (via TDH.VP.INIT), the vCPU
index is initialized in the %ecx register, while %esi is initialized to 0.

If %esi is used, will all vCPUs evaluate to index 0, causing them to
incorrectly share the same stack and guest code pointer? This seems like it
could corrupt the SMP stack and fail multi-vCPU tests.

[ ... ]

> +	/*
> +	 * Set up control registers (x86 does not support moving memory
> +	 * directly to a control register).
> +	 */
> +	movl TD_BOOT_PARAMETERS_CR4(%ebx), %edi
> +	movl %edi, %cr4
> +	movl TD_BOOT_PARAMETERS_CR3(%ebx), %edi
> +	movl %edi, %cr3
> +	movl TD_BOOT_PARAMETERS_CR0(%ebx), %edi
> +	movl %edi, %cr0
> +
> +	/* Switching to 64bit mode after ljmp and then jump to guest code */
> +	ljmp $(KERNEL_CS),$1f

[Severity: Medium]
Does td_boot miss a wrmsr to set EFER.LME before enabling paging?

The TDX VM guest boot code enables paging (CR0.PG) and physical address
extensions (CR4.PAE) here, but appears to omit writing the EFER MSR to set
the Long Mode Enable (LME) bit.

According to the x86 architecture, enabling paging without setting EFER.LME
puts the processor into 32-bit PAE paging mode instead of 64-bit IA-32e
mode.

Will the subsequent far jump attempt to load a 64-bit code segment
(KERNEL_CS has L=1), causing a #GP fault since it is invalid in 32-bit mode?
It seems this might crash the guest VM unconditionally on every boot.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261001-tdx-selftests-v15-0-7c62a5d8a992@google.com?part=7